4.4. Clocking Scheme

JESD204B Intel® FPGA IP User Guide

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Date 7/19/2024

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4.4. Clocking Scheme

This section describes the clocking scheme for the JESD204B IP core and transceiver.

Table 23. JESD204B IP Core Clocks
Clock Signal	Formula	Description
TX/RX Device Clock: `pll_ref_clk`	PLL selection during IP core generation	The PLL reference clock used by the TX Transceiver PLL or RX CDR. This is also the recommended reference clock to the PLL Intel® FPGA IP core (for Arria® V, Cyclone® V, or Stratix® V devices) or IOPLL Intel® FPGA IP core (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices).
TX/RX Link Clock: `txlink_clk` `rxlink_clk`	Data rate/40	The timing reference for the JESD204B IP core. The link clock runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding. For Subclass 1, to avoid half link clock latency variation, you must supply the device clock at the same frequency as the link clock. The JESD204B transport layer in the design example requires both the link clock and frame clock to be synchronous.
TX/RX Frame Clock (in design example): `txframe_clk` `rxframe_clk`	Data rate/(10 × F)	The frame clock as per the JESD204B specification. This clock is applicable to the JESD204B transport layer and other upstream devices that run in frame clock such as the PRBS generator/checker or any data processing blocks that run at the same rate as the frame clock. The JESD204B transport layer in the design example also supports running the frame clock in half rate or quarter rate by using the FRAMECLK_DIV parameter. The JESD204B transport layer requires both the link clock and frame clock to be synchronous. For more information, refer to the F1/F2_FRAMECLK_DIV parameter description and its relationship to the frame clock in the respective JESD204B Intel® FPGA IP design example user guides.
TX/RX Transceiver Serial Clock and Parallel Clock	Internally derived from the data rate during IP core generation	The serial clock is the bit clock to stream out serialized data. The transceiver PLL supplies this clock and is internal to the transceiver. The parallel clock is for the transmitter PMA and PCS within the PHY. This clock is internal to the transceiver and is not exposed in the JESD204B IP core. For Arria® V, Cyclone® V, and Stratix® V devices, these clocks are internally generated as the transceiver PLL is encapsulated within the JESD204B IP core's PHY. For Arria® 10, Cyclone® 10 GX, and Stratix® 10 L-tile and H-tile devices, you need to generate the transceiver PLL based on the data rate and connect the serial and parallel clock. You are recommended to select medium bandwidth for the transceiver PLL setting. These clocks are referred to as `serial_clk` and `bonding_clock` in Arria® 10, Cyclone® 10 GX, and Stratix® 10 L-tile and H-tile devices. Refer to the respective Transceiver PHY IP Core User Guides for more information.
TX/RX PHY Clock: `txphy_clk` `rxphy_clk`	Data rate/40 (for all devices except Arria V GT/ST in PMA Direct mode) Data rate/80 (for Arria V GT/ST devices in PMA Direct mode)	The PHY clock generated from the transceiver parallel clock for the TX path or the recovered clock generated from the CDR for the RX path. There is limited use for this clock. Avoid using this clock when PMA Direct mode is selected. Use this clock only if the JESD204B configuration is F=4 and the core is operating at Subclass 0 mode. This clock can be used as input for both the `txlink_clk` and `txframe_clk`, or `rxlink_clk` and `rxframe_clk`. When you set the PCS option to enable Hard PCS or Soft PCS mode, the `txphy_clk` connects to the transceiver `tx_std_clkout` signal and the `rxphy_clk` connects to the `rx_std_clkout` signal. These are the clock lines at the PCS and FPGA fabric interface. When you enable PMA Direct mode (for Arria V GT/ST only), the `txphy_clk` connects to the transceiver `tx_pma_clkout` signal and the `rxphy_clk` connects to the `rx_pma_clkout` signal. These are the clock lines at the PMA and PCS interface.
TX/RX AVS Clock: `jesd204_tx_avs_clk` `jesd204_rx_avs_clk`	75–125 MHz	The configuration clock for the JESD204B IP core CSR through the Avalon® memory-mapped interface.
Transceiver Management Clock: `reconfig_clk`	100 MHz–125 MHz ( Arria® 10) 100 MHz–125 MHz ( Cyclone® 10 GX) 100 MHz–150 MHz ( Stratix® 10)	The configuration clock for the transceiver CSR through the Avalon® memory-mapped interface. This clock is exported only when the transceiver dynamic reconfiguration option is enabled. This clock is only applicable for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.