JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

4.4. Clocking Scheme

This section describes the clocking scheme for the JESD204B IP core and transceiver.

Table 23.   JESD204B IP Core Clocks
Clock Signal Formula Description

TX/RX Device Clock:

pll_ref_clk

PLL selection during IP core generation The PLL reference clock used by the TX Transceiver PLL or RX CDR.

This is also the recommended reference clock to the PLL Intel® FPGA IP core (for Arria® V, Cyclone® V, or Stratix® V devices) or IOPLL Intel® FPGA IP core (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices).

TX/RX Link Clock:

txlink_clk

rxlink_clk

Data rate/40 The timing reference for the JESD204B IP core. The link clock runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/10B encoding.

For Subclass 1, to avoid half link clock latency variation, you must supply the device clock at the same frequency as the link clock.

The JESD204B transport layer in the design example requires both the link clock and frame clock to be synchronous.

TX/RX Frame Clock (in design example):

txframe_clk

rxframe_clk

Data rate/(10 × F) The frame clock as per the JESD204B specification. This clock is applicable to the JESD204B transport layer and other upstream devices that run in frame clock such as the PRBS generator/checker or any data processing blocks that run at the same rate as the frame clock.

The JESD204B transport layer in the design example also supports running the frame clock in half rate or quarter rate by using the FRAMECLK_DIV parameter. The JESD204B transport layer requires both the link clock and frame clock to be synchronous. For more information, refer to the F1/F2_FRAMECLK_DIV parameter description and its relationship to the frame clock in the respective JESD204B Intel® FPGA IP design example user guides.

TX/RX Transceiver Serial Clock and Parallel Clock Internally derived from the data rate during IP core generation The serial clock is the bit clock to stream out serialized data. The transceiver PLL supplies this clock and is internal to the transceiver.

The parallel clock is for the transmitter PMA and PCS within the PHY. This clock is internal to the transceiver and is not exposed in the JESD204B IP core.

For Arria® V, Cyclone® V, and Stratix® V devices, these clocks are internally generated as the transceiver PLL is encapsulated within the JESD204B IP core's PHY.

For Arria® 10, Cyclone® 10 GX, and Stratix® 10 L-tile and H-tile devices, you need to generate the transceiver PLL based on the data rate and connect the serial and parallel clock. You are recommended to select medium bandwidth for the transceiver PLL setting. These clocks are referred to as *serial_clk and *bonding_clock in Arria® 10, Cyclone® 10 GX, and Stratix® 10 L-tile and H-tile devices. Refer to the respective Transceiver PHY IP Core User Guides for more information.

TX/RX PHY Clock:

txphy_clk

rxphy_clk

Data rate/40 (for all devices except Arria V GT/ST in PMA Direct mode)

Data rate/80 (for Arria V GT/ST devices in PMA Direct mode)

The PHY clock generated from the transceiver parallel clock for the TX path or the recovered clock generated from the CDR for the RX path.

There is limited use for this clock. Avoid using this clock when PMA Direct mode is selected. Use this clock only if the JESD204B configuration is F=4 and the core is operating at Subclass 0 mode. This clock can be used as input for both the txlink_clk and txframe_clk, or rxlink_clk and rxframe_clk.

When you set the PCS option to enable Hard PCS or Soft PCS mode, the txphy_clk connects to the transceiver tx_std_clkout signal and the rxphy_clk connects to the rx_std_clkout signal. These are the clock lines at the PCS and FPGA fabric interface. When you enable PMA Direct mode (for Arria V GT/ST only), the txphy_clk connects to the transceiver tx_pma_clkout signal and the rxphy_clk connects to the rx_pma_clkout signal. These are the clock lines at the PMA and PCS interface.

TX/RX AVS Clock:

jesd204_tx_avs_clk

jesd204_rx_avs_clk

75–125 MHz The configuration clock for the JESD204B IP core CSR through the Avalon® memory-mapped interface.

Transceiver Management Clock:

reconfig_clk

100 MHz–125 MHz ( Arria® 10)

100 MHz–125 MHz ( Cyclone® 10 GX)

100 MHz–150 MHz ( Stratix® 10)

The configuration clock for the transceiver CSR through the Avalon® memory-mapped interface. This clock is exported only when the transceiver dynamic reconfiguration option is enabled.

This clock is only applicable for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.


Section Content
Device Clock
Link Clock
Local MultiFrame Clock
Clock Correlation
Transceiver Calibration Clock Source

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