JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

3.8.4. Timing Constraints For Input Clocks

When you generate the JESD204B IP variation, the Quartus® Prime software generates a Synopsys Design Constraints File (.sdc) that specifies the timing constraints for the input clocks to your IP.

When you generate the JESD204B IP, your design is not yet complete and the JESD204B IP is not yet connected in the design. The final clock names and paths are not yet known. Therefore, the Quartus® Prime software cannot incorporate the final signal names in the .sdc file that it automatically generates. Instead, you must manually modify the clock signal names in this file to integrate these constraints with the timing constraints for your full design.

This section describes how to integrate the timing constraints that the Quartus® Prime software generates with your IP into the timing constraints for your design.

The Quartus® Prime software automatically generates the altera_jesd204.sdc file that contains the JESD204B IP's timing constraints.

Three clocks are created at the input clock port:
  • JESD204B TX IP:
    • txlink_clk
    • reconfig_to_xcvr[0] (for Arria® V, Cyclone® V, and Stratix® V devices only)
    • reconfig_clk (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices only)
    • tx_avs_clk
  • JESD204B RX IP:
    • rxlink_clk
    • reconfig_to_xcvr[0] (for Arria® V, Cyclone® V, and Stratix® V devices only)
    • reconfig_clk (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices only)
    • rx_avs_clk
In a functional system design, these clocks (except for reconfig_to_xcvr[0] clock) are typically provided by the core PLL.

In the .sdc file for your project, make the following command changes:

  • Specify the PLL clock reference pin frequency using the create_clock command.
  • Derive the PLL generated output clocks from the PLL Intel® FPGA IP (for Arria V, Cyclone V and Stratix V) or IOPLL Intel® FPGA IP (for Arria® 10 and Cyclone® 10 GX) using the derive_pll_clocks command.
  • For Stratix® 10 devices, Intel® FPGA IOPLL IP core has SDC file which derives the PLL clocks based on your PLL configurations. You need not add the derive_pll_clocks command into your top level SDC file."
  • Comment out the create_clock commands for the txlink_clk, reconfig_to_xcvr[0] or reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks in the altera_jesd204.sdc file.
  • Identify the base and generated clock name that correlates to the txlink_clk, reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks using the report_clock command.
  • Describe the relationship between base and generated clocks in the design using the set_clock_groups command.

After you complete your design, you must modify the clock names in your .sdc file to the full-design clock names, taking into account both the IP instance name in the full design, and the design hierarchy. Be careful when adding the timing exceptions based on your design, for example, when the JESD204B IP handles asynchronous timing between the txlink_clk, rxlink_clk, pll_ref_clk, tx_avs_clk, rx_avs_clk, and reconfig_clk (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices only) clocks.

The table below shows an example of clock names in the altera_jesd204.sdc and input clock names in the user design. In this example, there is a dedicated input clock for the transceiver TX PLL and CDR at the refclk pin. The device_clk is the input to the core PLL clkin pin. The IP and transceiver Avalon® memory-mapped interfaces have separate external clock sources with different frequencies.

Table 13.  Example A
Original clock names in altera_jesd204.sdc User design input clock names Frequency (MHz) Recommended SDC timing constraint
tx_pll_ref_clk xcvr_tx_rx_refclk 250

create_clock -name xcvr_tx_rx_refclk -period 4.0 [get_ports xcvr_tx_rx_refclk ]

create_clock -name device_clk -period 8.0 [get_ports device_clk]

create_clock -name jesd204_avs_clk -period 10.0 [get_ports jesd204_avs_clk]

create_clock -name phy_mgmt_clk -period 13.3 [get_ports phy_mgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {xcvr_tx_rx_refclk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {device_clk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {jesd204_avs_clk} \

-group {phy_mgmt_clk \

<base and generated clock names as reported by report_clock commands> \

}
rx_pll_ref_clk
txlink_clk device_clk 125
rxlink_clk
tx_avs_clk jesd204_avs_clk 100
rx_avs_clk
reconfig_clk 16 phy_mgmt_clk 75

However, if your design requires you to connect the rx_avs_clk and reconfig_clk to the same clock, you need to put them in the same clock group.

The table below shows an example where the device_clk in this design is an input into the transceiver refclk pin. The IP's Avalon® memory-mapped interface shares the same clock source as the transceiver management clock.

Table 14.  Example B
Original clock names in altera_jesd204.sdc User design input clock names Frequency (MHz) Recommended SDC timing constraint
tx_pll_ref_clk device_clk 125

create_clock -name device_clk -period 8.0 [get_ports device_clk]

create_clock -name mgmt_clk -period 10.0 [get_ports mgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {device_clk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {mgmt_clk \

<base and generated clock names as reported by report_clock commands> \

}
rx_pll_ref_clk
txlink_clk
rxlink_clk
tx_avs_clk mgmt_clk 100
rx_avs_clk
reconfig_clk 17
16 For Arria® 10, Cyclone® 10 GX, and Stratix® 10 only.
17 For Agilex™ 7, Stratix® 10, Cyclone® 10 GX, and Arria® 10 only.
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