JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 7/19/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

2.7. Performance and Resource Utilization

Table 8.   JESD204B Intel® FPGA IP Performance
Device Family PMA Speed Grade FPGA Fabric Speed Grade Data Rate Link Clock FMAX (MHz)
Enable Hard PCS (Gbps) Enable Soft PCS (Gbps) 4
Agilex™ 7 (E-tile) 1 –1 Not supported 2.0 to 19.2 data_rate/40
2 –2 Not supported 2.0 to 17.4 data_rate/40
–3 Not supported 2.0 to 16.0 data_rate/40
3 –2 Not supported 2.0 to 17.4 data_rate/40
–3 Not supported 2.0 to 16.0 data_rate/40
Stratix® 10 (L-tile, and H-tile) 1 –1 2.0 to 12.0 2.0 to 16.06 data_rate/40
–2 2.0 to 12.0 2.0 to 14.0 data_rate/40
2 –1 2.0 to 9.83 2.0 to 16.06 data_rate/40
–2 2.0 to 9.83 2.0 to 14.0 data_rate/40
3 –1 2.0 to 9.83 2.0 to 16.06 data_rate/40
–2 2.0 to 9.83 2.0 to 14.0 data_rate/40
–3 2.0 to 9.83 2.0 to 13.0 data_rate/40
Stratix® 10 (E-tile) 1 –1 Not supported 2.0 to 16.06 data_rate/40
–2 Not supported 2.0 to 14.0 data_rate/40
2 –1 Not supported 2.0 to 16.06 data_rate/40
–2 Not supported 2.0 to 14.0 data_rate/40
3 –1 Not supported 2.0 to 16.0 data_rate/40
–2 Not supported 2.0 to 14.0 data_rate/40
–3 Not supported 2.0 to 13.0 data_rate/40
Arria® 10 1 –1 2.0 to 12.0 2.0 to 15.0 6 5 data rate/40
2 –1 2.0 to 12.0 2.0 to 15.0 6 5 data rate/40
2 –2 2.0 to 9.83 2.0 to 15.0 6 5 data rate/40
3 –1 2.0 to 12.0 2.0 to 14.2 6 7 data rate/40
3 –2 2.0 to 9.83 2.0 to 14.2 6 8 data rate/40
4 –3 2.0 to 8.83 2.0 to 12.59 data rate/40
Cyclone® 10 GX 4 -5 2.0 to 9.8 10 2.0 to 9.810 data rate/40
-6 2.0 to 6.25 2.0 to 9.810 data rate/40
Stratix V 1 –1 or –2 2.0 to 12.2 2.0 to 12.5 data rate/40
2 –1 or –2 2.0 to 12.2 2.0 to 12.5 data rate/40
2 –3 2.0 to 9.8 2.0 to 12.5 11 data rate/40
3 –1, –2, –3, or –4 2.0 to 8.5 2.0 to 8.5 data rate/40
Arria V GX/SX <Any supported speed grade> <Any supported speed grade> 1.0 to 6.55 — 12 data rate/40
Arria V GT/ST <Any supported speed grade> <Any supported speed grade> 1.0 to 6.55 4.0 to 7.5

(PMA direct) 12

data rate/40
Arria V GZ 2 –3 2.0 to 9.9 — 12 data rate/40
3 –4 2.0 to 8.8 — 12 data rate/40
Cyclone V 5 <Any supported speed grade> 1.0 to 5.0 — data rate/40
6 –6 or –7 1.0 to 3.125 — data rate/40

The following table lists the resources and expected performance of the JESD204B IP core. These results are obtained using the Quartus® Prime software targeting the following Intel® FPGA devices:

  • Cyclone V: 5CGTFD9E5F31I7
  • Arria V GT/S/GT: 5AGXFB3H4F35C5
  • Arria V GZ: 5AGZME5K2F40C3
  • Stratix V: 5SGXEA7H3F35C3
  • Arria® 10: 10AX115H2F34I2SGES
  • Stratix® 10: 1SG280LN3F43E3VG
  • Cyclone® 10 GX: 10CX105YF672I6G

All the variations for resource utilization are configured with the following parameter settings:

Table 9.  Parameter Settings To Obtain the Resource Utilization Data
Parameter Setting
JESD204B Wrapper Base and PHY
JESD204B Subclass 1
Data Rate 5 Gbps
PCS Option Enabled Hard PCS
PLL Type
  • ATX (for Arria® 10, Cyclone® 10 GX, and Stratix® 10 L-tile and H-tile devices)
  • CMU (for Arria V, Cyclone V, and Stratix V devices)
Bonding Mode Non-bonded
Reference Clock Frequency 125.0 MHz
Octets per frame (F)
  • 1 (For all devices, including Stratix® 10)
  • 3 (For Stratix® 10 device only)
Enable Scrambler (SCR) Off
Enable Error Code Correction (ECC_EN) Off
Table 10.   JESD204B IP Core Resource Utilization
Note: The resource utilization data are extracted from a full design which includes the Intel® FPGA Transceiver PHY Reset Controller IP core. Thus, the actual resource utilization for the JESD204B IP core should be smaller by about 15 ALMs and 20 registers.
Device Family Data Path Number of Lanes (L) ALMs ALUTs Logic Registers Memory Block (M10K/M20K) 13 14
Stratix® 10

(F=1)

 RX 1 889.4 1230 1334 0
2 1329.7 1810 2119 0
4 2302.8 3101 3634 0
8 4218.1 5638 6650 0
TX 1 534.4 694 869 0
2 746 1061 1078 0
4 1049.8 1557 1580 0
8 1534.2 1980 2507 0
Stratix® 10

(F=3)

 RX 1 905.1 1336 1453 1
2 1431.5 2102 2281 2
4 2445.9 3487 3899 4
8 4568 6592 6870 8
TX 1 568.7 737 907 0
2 790.2 1126 1126 0
4 1096.4 1659 1545 0
8 1617.1 2082 2524 0
Arria® 10 RX 1 1047 1496 1264 0
2 1584 2262 1903 0
4 2884.5 3870 3211 0
8 5339 7196 5768 0
TX 1 701.5 1090 989 0
2 875.5 1341 1126 0
4 1248.5 1888 1382 0
8 1917.5 2820 1878 0
Cyclone® 10 GX RX 1 1020.5 1496 1250 1
2 1551.5 2262 1877 2
4 2801 3870 3159 4
8 5173.5 7196 5749 8
TX 1 710 1090 989 0
2 875.4 1341 1118 0
4 1249 1888 1369 0
8 1926.5 2820 1869 0
Stratix V RX 1 1047.2 1530 1225 0
2 1608.7 2322 1871 0
4 2897.2 4037 3161 0
8 5412.5 7506 5742 0
TX 1 711 1152 948 0
2 926.7 1491 1086 0
4 1345.7 2134 1361 0
8 2114.7 3358 1907 0
Arria V RX 1 1024.5 1516 1207 1
2 1555.5 2302 1838 2
4 2769.5 3951 3102 4
8 5189 7399 5619 8
TX 1 711.7 1149 948 0
2 860.5 1418 1065 0
4 1188.7 1932 1299 0
8 1721 2854 1767 0
Arria V GZ RX 1 1048.7 1530 1226 0
2 1601.5 2322 1870 0
4 2894 4037 3163 0
8 5400.5 7506 5748 0
TX 1 712.2 1152 948 0
2 926.5 1491 1087 0
4 1349.2 2134 1359 0
8 2104.7 3358 1907 0
Cyclone V RX 1 1022 1516 1210 1
2 1555.5 2302 1839 2
4 2777.5 3951 3099 4
8 5195 7399 5619 8
TX 1 713.5 1149 948 0
2 867 1418 1066 0
4 1198 1932 1300 0
8 1709.2 2838 1769 0
Related Information
4 Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization.
5 When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.
6 Refer to the Arria® 10 and Stratix® 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.
7 For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.
8 For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.
9 For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.
10 Chip-to-chip applications only. Backplane only supports data rates up to 6.25 Gbps
11 When using Soft PCS mode at 12.5 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.
12 Enabling Soft PCS does not increase the data rate for the device family and speed grade. You are recommended to select the Enable Hard PCS option.
13 M10K for Arria V, Cyclone V devices, M20K for Arria V GZ, Stratix V, Arria® 10, Cyclone® 10 GX, and Stratix® 10 devices.
14

The Quartus® Prime software may auto-fit to use MLAB when the memory size is too small. Conversion from MLAB to M20K or M10K was performed for the numbers listed above.

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