JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 12/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.12.13 24.2 20.2.1 Updated data rate for Cyclone® 10 GX in section:
  • Performance and Resource Utilization
  • JESD204B Intel® FPGA IP Parameters
2024.07.19 24.2 20.2.1
  • Removed Nios® II support.
  • Updated data rate for Cyclone® 10 GX in section:
    • Performance and Resource Utilization
    • JESD204B Intel® FPGA IP Parameters
2023.07.20 23.2 20.1.0
  • Added a new section: SYSREF Guidelines.
  • Updated description in Link Startup Sequence to clarify TX (Subclass 1) and RX (Subclass 1).
  • Updated description in ADC-FPGA Subsystem Reset Sequence.
  • Updated description in FPGA-DAC Subsystem Reset Sequence.
  • Updated figures in Programmable RBD Offset section:
    • Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi Frame Scenario.
    • Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi Frames Scenario.
2023.06.26 23.2 20.1.0 Updated the ordering code in Table: JESD204B Intel® FPGA IP Release Information.
2023.05.05 21.3 19.2.0
  • Updated Related Information list in JESD204B IP Quick Reference.
  • Updated description in tables:
    • syncn_sysref_ctrl
      • Bit 10:3, csr_rbd_offset
    • rx_err0
      • Bit 4, csr_lane_deskew_err
2022.08.18 21.3 19.2.0
  • Fixed broken link to the E-Tile Channel Placement Tool in the Pin Assignments section.
  • Updated the JESD204B Intel® FPGA IP User Guide Archives section.
2022.05.18 21.3 19.2.0
  • Corrected IP Version from 19.3.0 to 19.2.0.
  • Corrected the Quartus® Prime Version and Release Date descriptions in Table: JESD204B IP Release Information.
2021.12.09 21.3 19.2.0 Corrected the support final for Agilex™ 7 (E-tile) devices from Advance to Final in Table: Intel Device Family Support.
2021.11.01 21.3 19.2.0
  • Updated the description for Control and Status Registers clarify that registers that are Read-Writable must be protected to comply with Security Development Lifecycle (SDL) practices.
  • Added support for QuestaSim* simulator.
  • Updated for latest branding standards.
2021.06.23 20.2 19.2.0
  • Updated Transceiver Calibration Clock Source to include information about the OSC_CLK_1 requirements for Agilex™ 7 and Stratix® 10 E-tile devices.
  • Removed support for NCSim in the following tables:
    • Table: Brief Information About the JESD204B IP
    • Table: Simulation Setup Scripts
    • Table: Simulation Run Scripts
2021.04.01 20.2 19.2.0
  • Updated Table: tx_status0 to correct the bit information for csr_dll_state and csr_dev_syncn.
2020.09.10 20.2 19.2.0
  • Added a new section, Transceiver Calibration Clock Source, which provides information about the OSC_CLK pin that provides the transceiver calibration clock source for Stratix® 10 L-tile and H-tile devices.
  • Corrected the reset value for the receiver csr_lane_alignment_err_link_reinit[13] and csr_lane_alignment_err_link_reinit[12] registers. The reset value should be 0x1, not 0x0.
  • Added a new section, Removing Irrelevant Signals and Adding E-Tile PHY Signals, which provides the steps to remove irrelevant PHY signals for Stratix® 10 E-tile designs.
  • Added a link to the Removing Irrelevant Signals and Adding E-Tile PHY Signals section in the Creating a Debug File to Match Your Design Hierarchy section.
2020.06.30 19.4 19.2.0
  • Added the supported data rate for PMA speed grade 2 for Agilex™ 7 E-tile devices and for PMA speed grade 3 for Stratix® 10 E-tile devices in the Performance and Resource Utilization section.
  • Corrected the offset address for the receiver lane_ctrl_1 register. The offset address should be 0x8, not 0xC.
2020.03.03 19.4 19.2.0 Edited the Enable Bit reversal and Byte reversal parameter description in the JESD204B Intel® FPGA IP Parameters section.
2019.12.16 19.4 19.2.0
  • Updated the supported maximum data rate to 19.2 Gbps (for Agilex™ 7 devices) in the JESD204B IP Quick Reference, About the JESD204B Intel® FPGA IP , and Performance and Resource Utilization sections.
  • Updated the maximum data rate value option to 19.2 Gbps for Agilex™ 7 devices for the Data Rate parameter and edited the Enable Bit reversal and Byte reversal parameter description in the JESD204B Intel® FPGA IP Parameters section.
2019.10.07 19.3 19.2.0
  • Added advance support for Agilex™ 7 devices.
  • Updated the supported maximum data rate to 17.4 Gbps (for Agilex™ 7 devices) in the JESD204B IP Quick Reference and About the JESD204B Intel® FPGA IP sections.
  • Updated the JESD204B Intel® FPGA IP Performance table in the Performance and Resource Utilization section with Agilex™ 7 devices information.
  • Updated the maximum data rate value option to 17.4 Gbps for Agilex™ 7 devices in the JESD204B Intel® FPGA IP Parameters section.
  • Added a reference link to the JESD204B Agilex™ 7 FPGA IP Design Example User Guide.
2019.05.27 19.1 19.1 Corrected typos in the Transmitter Registers and Receiver Registers sections; changed LEMC to LMFC.
2019.04.01 19.1 19.1
  • Added support for Stratix® 10 E-tile devices.
  • Revised the resource utilization data for version 19.1 in the Performance and Resource Utilization section.
  • Updated the JESD204B Intel® FPGA IP Performance table with Stratix® 10 E-tile device information in the Performance and Resource Utilization section.
  • Updated the Channel Bonding section to include information about Stratix® 10 E-tile devices. For Stratix® 10 E-tile devices, you must use contiguous channels to enable channel bonding with NRZ PMA transceiver channels.
  • Added the Transceiver Tile option which is available when you target an Stratix® 10 device that supports both and H-tile and E-tile.
  • Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel rebranding in the Quartus® Prime Pro Edition software. The Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint.
  • Added a note to refer to the PMA Adaptation section in the Intel Stratix 10 E-tile Transceiver PHY User Guide for more information about PMA Adaptation parameters.
  • Edited the Transmitter Signals and Receiver Signals sections to add a note that certain signals are not applicable for Stratix® 10 E-tile devices or applicable only for Stratix® 10 L-tile and H-tile devices.
  • Added the following signals that are applicable only for Stratix® 10 E-tile devices in the Transmitter Signals and Receiver Signals sections:
    • phy_tx_ready
    • phy_rx_ready
    • phy_tx_pma_ready
    • phy_rx_pma_ready
    • phy_tx_rst_n
    • phy_rx_rst_n
    • tx_serial_data_n
    • rx_serial_data_n
  • Added a note in the Pin Assignments section to use the E-Tile Channel Placement Tool to get a valid pinout for Stratix® 10 E-tile devices.
  • Added a note in the Adding External Transceiver PLLs section that Stratix® 10 E-tile device designs do not require external PLLs.
  • Added a note in the Simulating the IP Core Testbench section that Stratix® 10 E-tile devices do not support the Riviera-PRO* simulator.
  • Add information about Stratix® 10 E-tile devices in the Testbench Simulation Flow section.
  • Edited the Creating a Debug File to Match Your Design Hierarchy section to add information about Stratix® 10 E-tile devices.
  • Edited the Debugging JESD204B Link Using System Console section to add information about Stratix® 10 E-tile devices.
  • Added the Transmitter Registers and Receiver Registers sections in the Registers chapter. The register information are now available in the document.
2018.12.10 18.1 18.1
  • Updated the Device Family Support section to indicate that the JESD204B Intel® FPGA IP core supports only Stratix® 10 (L-tile and H-tile) devices.
  • Revised the data rate information for Stratix® 10 devices for speed grade 2 and 3.
  • Revised the resource utilization data and speed grade information for version 18.1.
  • Added resource utilization data and speed grade information for Stratix® 10 devices when number of octets per frame (F) is 3.
  • Updated the Octets per frame (F) parameter option to support F=3 in the JESD204B IP Core Parameter section. F=3 is available only for Stratix® 10 devices.
  • Categorized the following signals as debug and testing signals in the Transmitter Signals section:
    • csr_tx_testmode[3:0]
    • csr_tx_testpattern_a[]
    • csr_tx_testpattern_b[]
    • csr_tx_testpattern_c[]
    • csr_tx_testpattern_d[]
  • Categorized the csr_rx_testmode[3:0] signal as a debug and testing signal in the Receiver Signals section.
  • Added a note in the Receiver Signals section that the test pattern checker is a component in the design example and is not a part of the JESD204B IP core
  • Added a note in the Transmitter Signals section that the test pattern generator is a component in the design example and is not a part of the JESD204B IP core
  • Edited the steps for running analysis and synthesis in the Creating a Signal Tap Debug File to Match Your Design section.
2018.05.07 18.0 18.0
  • Renamed JESD204B IP core to JESD204B Intel® FPGA IP as per Intel rebranding.
  • Added support for Cyclone® 10 GX devices.
  • Added simulation setup and run scripts for the Cadence Xcelium* Parallel simulator.
  • Added links to the JESD204B Intel® FPGA IP Design Example for Cyclone® 10 GX Devices User Guide.
  • Edited a typo in in the Brief Information About the JESD204B IP Core table. Changed Platform Designer (Standard) to Platform Designer.
  • Revised the resource utilization data and speed grade information for version 18.0.
  • Updated the JESD204B IP Core Parameters and Signals sections with Cyclone® 10 GX information.
  • Edited the steps in the Creating a Signal Tap Debug File to Match Your Design Hierarchy section.
  • Added a note in the Testbench Simulation Flow section that for Stratix® 10 devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready.
Date Version Changes
November 2017 2017.11.06
  • Updated alldev_lane_aligned signal description.
  • Updated bonded channel requirements for Stratix® 10 and Arria® 10 devices.
  • Updated instances of Qsys to Platform Designer.
  • Updated steps to simulate the testbench design using the Aldec Riviera-PRO simulator.
  • Removed note stating that the dynamic reconfiguration is not supported for the JESD204B IP core testbench.
  • Added Base only, or Simplex TX configuration in Preset Configurations for JESD204B IP Core Testbench table.
  • Added Provide Separate Reconfiguration Interface for Each Channel parameter in the JESD204B IP Core Parameters table.
  • Updated Link Clock FMAX (MHz) for all devices in the JESD204B IP Core FPGA Performance table.
  • Added supported data rate note to Arria® 10 variants in JESD204B IP Core FPGA Performance table.
  • Updated rx_phy and tx_phy assignments in Creating a Signal Tap Debug File to Match Your Design Hierarchy.
  • Updated the data rate support for Stratix® 10 devices:
    • For speed grade 1 to up to 16.0 Gbps.
    • For speed grade 2 to up to 13.5 Gbps.
    • For speed grade 3 to up to 12.5 Gbps.
  • Updated and added example timing diagrams in Subclass 2 Operating Mode subsection.
  • Updated transceiver interface signals for transmitter and receiver signals.
May 2017 2017.05.08
  • Updated description for PLL/CDR Reference Clock Frequency in JESD204B IP Core Parameters.
  • Added somf[] for transmitter signal.
  • Updated Run-Time Configuration to include statement on JESD204B IP core parameterization for Stratix® 10 devices.
  • Added note to Registers to indicate that disabled run-time access for registers in Stratix® 10 devices.
  • Updated data path preset value to simplex TX and simplex RX in Preset Configurations for JESD204B IP Core Testbench table.
  • Clarified the device family support for Stratix 10 devices.
  • Added Transmitter and Receiver signal diagrams.
  • Added Share Reconfiguration Interface parameter in JESD204B IP Core Parameters table.
  • Added note and description to Share Reconfiguration Interface in JESD204B IP Core Parameters.
  • Added links to Stratix 10 device Datasheet, Stratix 10 L-Tile Transceiver PHY User Guide, and Stratix 10 H-Tile Transceiver PHY User Guide.
  • Added tx_analogreset_stat, rx_analogreset_stat, tx_digitalreset_stat, and rx_digitalreset_stat signals and descriptions.
  • Updated ADC-FPGA Subsystem Reset Scheme and FPGA-DAC Subsystem Reset Scheme.
October 2016 2016.10.31
  • Updated Example 2 in Clock Correlation.
  • Updated steps in FPGA–DAC Subsystem Reset Sequence.
  • Updated figure and title for JESD204B Subsystem with Shared Transceiver Reference Clock and Core Clock and JESD204B Subsystem with Separate Transceiver Reference Clock and Core Clock.
  • Updated Subclass 1 Deterministic Latency and Support for Programmable Release Opportunity figure.
  • Updated Channel Bonding description.
May 2016 2016.05.02
  • Updated the IP Core release information.
  • Updated the data rate support—uncharacterized support for data rates of up to 15 Gbps.
  • Updated the data rate for Arria® 10 and Arria V GT/ST in the JESD204B IP Core FPGA Performance table.
  • Updated the JESD204B IP Core FPGA Resource Utilization table.
  • Updated the PLL/CDR Reference Clock Frequency parameter description.
  • Updated the preset values for PLL/CDR Reference Clock Frequency, Link Clock, and AVS Clock in Table 3-8: Preset Configurations for JESD204B IP Core Testbench.
  • Updated Figure 4-8 to illustrate shared clocking and renamed the title to "JESD204B Subsystem with Shared Transceiver Reference Clock and Core Clock".
  • Added a new figure to illustrate separate clocking—Figure 4-9: JESD204B Subsystem with Separate Transceiver Reference Clock and Core Clock.
  • Added new sections:
  • Updated the TX path CONTROL_BUS_ WIDTH parameter description.
  • Revised the clock domain for jesd204_tx_data_ready signal to txframe_clk.
  • Updated the description for the following registers in the register map:
    • rx_regmap:
      • csr_frame_data_ready_err
      • csr_pcfifo_full_err
      • csr_pcfifo_empty_err
    • tx_regmap:
      • csr_pcfifo_full_err
      • csr_pcfifo_empty_err
  • Added links to archived document in JESD204B Intel FPGA IP User Guide Archives.
November 2015 2015.11.02
  • Added data rate support of up to 13.5 Gbps for Arria® 10 and 7.5 Gbps for Arria V GT/ST devices.
  • Updated the IP core FPGA performance and resource utilization values.
  • Added a new table to define the clock network selection for bonded mode in channel bonding.
  • Added a new selection for PCS Option parameter—Enabled PMA Direct.
  • Updated the preset value for link clock in JESD204B IP Testbench.
  • Updated the formula and description for TX/RX PHY clock.
  • Updated the device clock section to recommend user to supply the device clock with the same frequency as the link clock.
  • Updated the description of txlink_clk, txphy_clk[], and rxphy_clk[] signals.
  • Changed the default value for RX Phase Compensation FIFO empty error enable (csr_pcfifo_empty_err_en) CSR to 0. Refer to the RX register map for details.
  • Added a new section—Design Example with Nios II Processor Control Unit.
  • Added a new topic – Maintaining Deterministic Latency during Link Reinitialization.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Added support for Cyclone V FPGA device family.
  • Updated the JESD204B IP Core Configuration values:
    • M value from 1-32 to 1-256
    • N' value from 4-32 to 1-32
  • Updated the JESD204B IP Core FPGA Performance table.
  • Updated the JESD204B IP Core FPGA Resource Utilization table.
  • Added new parameters to the JESD204B IP Core Parameters table:
    • Enable Capability Registers
    • Set user-defined IP identifier
    • Enable Control and Status Registers
    • Enable Prbs Soft Accumulators
    • Enable manual F configuration
  • Added new topics:
  • Revised the note in "Simulating the IP Core Testbench" to state that VHDL is not supported in Aldec Riviera (for Arria® 10 devices only).
  • Updated the Control Unit Process Flow diagram.
December 2014 2014.12.15
  • Updated the JESD204B IP Core FPGA Performance table with the data rate range.
  • Updated the JESD204B IP Core FPGA Resource Utilization table.
  • Updated the JESD204B IP Core Parameters table with the following changes:
    • Revised the parameter name of Enable PLL/CDR Dynamic Reconfiguration to Enable Transceiver Dynamic Reconfiguration.
    • Added information for a new parameter—Enable Altera Debug Master Endpoint.
    • Added details about the rule check for parameter N' value.
  • Added a new topic—Integrating the JESD204B IP in Platform Designer.
  • Updated Overview of the JESD204B IP Core Block Diagram, Transmitter Data Path Block Diagram, and Receiver Data Path Block Diagram.
  • Added a new table—Register Access Type Convention—to describe the access type for the IP core registers.
  • Added new signals description for jesd204_tx_controlout and jesd204_rx_controlout.
  • Added CONTROL_BUS_WIDTH parameter and description for the assembler and deassembler.
  • Added information on how to run the Tcl script using the Quartus II software before compiling the design example.
  • Updated the section on Debugging JESD204B Link Using System Console with verification information for TX PHY-link layer interface, TX link layer, and TX transport layer operations.
June 2014 2014.06.30
  • Updated Figure 2-1 to show a typical system application.
  • Updated the list of core key features.
  • Updated the Performance and Resource utilization values.
  • Updated the Getting Started chapter to reflect the new IP Catalog and parameter editor.
  • Added the following new sections to further describe the JESD204B IP core features:
    • Channel Bonding
    • Datapath Modes
    • IP Core Variation
    • JESD204B IP Core Testbench
    • JESD204B IP Core Design Considerations
    • TX Data Link Layer
    • TX PHY Layer
    • RX Data Link Layer
    • RX PHY Layer
    • Operation
    • Dynamic Reconfiguration
    • JESD204B IP Core Debug Guidelines
  • Updated the Clocking scheme section.
  • Added new transceiver signals that is supported in Arria® 10 devices.
  • Updated the Transport Layer section.
  • Added run-time reconfiguration parameter values in the System Parameters section.
  • Updated the file directory names.
November 2013 2013.11.04 Initial release.
Level Two Title