Visible to Intel only — GUID: lmb1620227494624
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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 7 SoC FPGA Boot Flow
8. SoC FPGA Boot User Guide Archives
9. Document Revision History for Agilex™ 7 SoC FPGA Boot User Guide
A. Boot Scratch Registers
4.1. Overview
4.2. Quartus® Prime Hardware Project Compilation
4.3. Bootloader Software Compilation
4.4. Programming File Generator
4.5. Configuration over JTAG
4.6. Configuration from QSPI
4.7. Configuration over AVST
4.8. Configuration via Protocol
4.9. Remote System Update
4.10. Partial Reconfiguration
A.1. BOOT_SCRATCH_COLD0
A.2. BOOT_SCRATCH_COLD1
A.3. BOOT_SCRATCH_COLD2
A.4. BOOT_SCRATCH_COLD3
A.5. BOOT_SCRATCH_COLD4, BOOT_SCRATCH_COLD5
A.6. BOOT_SCRATCH_COLD6, BOOT_SCRATCH_COLD7
A.7. BOOT_SCRATCH_COLD8
A.8. BOOT_SCRATCH_COLD9
A.9. BOOT_SCRATCH_COLD0, BOOT_SCRATCH_COLD1, BOOT_SCRATCH_COLD8, BOOT_SCRATCH_COLD9
Visible to Intel only — GUID: lmb1620227494624
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4.2.1. Device and Pin Options
The device and pin options can be accessed from Quartus® Prime, by going to Assignments > Device > Device and Pin Options. The most important options related to configuration and HPS boot are:
- General > Configuration Clock Source : allows using an internal oscillator or an external input clock for configuration purposes.
- Configuration > Configuration Scheme: allows selecting the configuration source:
- Active Serial x4
- AVST x8
- AVST x16
- AVST x32
- Configuration > Active Serial Clock Source: allows selecting the QSPI clock speed when Active Serial x4 mode is selected
- Configuration > Configuration Pin Options: allows selecting SDM pin behavior for configuration purposes
- Configuration > HPS/FPGA Configuration Order: allows selecting FPGA Configuration First (called After INIT_DONE) or HPS Boot First (called HPS First) modes.
- Configuration > HPS Debug Access Port (DAP): allows the HPS JTAG port to be connected to HPS Pins, FPGA Pins or Disabled. It is typically connected to SDM pins, so you can have a single JTAG connection covering both SDM and HPS.
- CvP Settings > Configuration via Protocol: can be selected as Initialization and update or Off.
For more information about these options, refer to the Agilex™ 7 Configuration User Guide.