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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
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2.2.3. Single SDM Flash
In a single flash attached to SDM layout, the flash contains all of the files required for booting, including the configuration bitstream and OS files.
SDM Flash Type | Details |
---|---|
Active serial/Quad SPI | Supported in a future version of the SoC EDS. |
Software running on the HPS such as the FSBL) must request permission from the SDM to access the flash attached to the SDM.
In the Quad SPI flash example, the SSBL, OS and file system reside in the Unsorted Block Image File System (UBIFS).
Figure 4. FPGA Configuration First Layout with Quad SPI