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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
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7.1. Reset
Reset Type | Initiated By | Details |
---|---|---|
Power-on Reset | An external event |
|
nCONFIG Reset | nCONFIG pin | An SoC device-wide reset input that cold resets the HPS and reconfigures the FPGA. |
Cold Reset |
|
|
Cold and Trigger Remote Update Reset | Watchdog Timeout Event (calls SDM) |
|
Warm Reset |
|
|
Software Reset | A software write to the Reset Manager |
|
Watchdog Reset | Timeout from a user configurable watchdog timer register. |
|
Debug Reset | JTAG SRST pin |
|
JTAG Reset | JTAG SRST pin |
|
When the device is reset in secure mode, all system warm and watchdog resets are treated as a POR reset. When the HPS is released from reset, all CPUs begin executing the FSBL. The FSBL ensures that CPUs 1 through 3 are in wait-for-interrupt (WFI) mode.
3 The Cortex* -A53 has four levels of exception from EL3 to EL0. EL3 is the highest privilege and EL0 is the lowest.