Intel® Agilex™ SoC FPGA Boot User Guide

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ID 683389
Date 11/10/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
1. Introduction x
1.1. Glossary 1.2. Intel® Agilex™ SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update
4.2. Intel® Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide

6.2. Configuring the FPGA Fabric from Linux

Note: This feature is supported with Linux* kernel v4.9 LTSI and onwards. Refer to RocketBoards.org and the Intel® public git repository for the latest information regarding this feature.

The Linux* kernel for Intel® Agilex™ SoC FPGA allows you to enable the programming of FPGA from within the OS.

If you want to test the FPGA reconfiguration at kernel level, make the following changes to the kernel source code:
  1. In the file arch/arm64/boot/dts/intel/Makefile, add a second .dtb file. For example: 
    dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb
dtb-$(CONFIG_ARCH_AGILEX) += overlay.dtb
  2. Create the new overlay.dts file and add the overlay information of the RBF file into the file as shown below:
    /dts-v1/;
/plugin/;
/ {
	fragment@0 {
		target-path = "/soc/base_fpga_region";
		#address-cells = <1>;
		#size-cells = <1>;
		__overlay__ {
			#address-cells = <1>;
			#size-cells = <1>;

			firmware-name = "overlay.dtb";
			config-complete-timeout-us = <30000000>;
		};
	};
};

When you build the Linux* kernel for this feature, the build generates two *.dtb files.

Table 19.  Resultant Files
Device Tree File Description
socfpga_agilex_socdk.dtb The default *.dtb file used with the kernel image to boot the system.
overlay.dtb The *.dtb file used to trigger FPGA configuration in OS.

In your compilation output folder, rename the FPGA configuration file (*.rbf) to the following name: overlay.rbf. Then, copy both the FPGA configuration file (*.rbf) and the overlay.dtb file to the following location in your Root File System: 

$ mkdir <your_ROOTFS>/lib/firmware

$ cp overlay.dtb <your_ROOTFS>/lib/firmware/

$ cp overlay.rbf <your_ROOTFS>/lib/firmware/

The changes above allow you to program the FPGA in Linux* by applying an overlay on the system. After you boot to Linux* and log in with root privilege, use the following command to begin FPGA configuration: 

# mkdir /sys/kernel/config/device-tree/overlays/0

# echo overlay.dtb >

/sys/kernel/config/device-tree/overlays/0/path/
If you want to re-apply the overlay, you have to first remove the existing overlay, and then re-run the previous steps: 
# rmdir /sys/kernel/config/device-tree/overlays/0

# mkdir /sys/kernel/config/device-tree/overlays/0

# echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path

The following design example demonstrates using Linux device tree overlays to configure the FPGA fabric: Intel® Agilex™ SoC HPS First Single QSPI Flash Boot.

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