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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
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2.2.1. External Configuration Host Only
Figure 2. External Configuration Host Only
In this example, the external configuration host ( Avalon® streaming or JTAG) provides the SDM with a configuration bitstream that consist of:
- SDM configuration firmware
- FPGA I/O and HPS EMIF I/O configuration data
- FPGA core configuration data
- HPS FSBL code and HPS FSBL hardware handoff binary
SDM Configuration Host | Details |
---|---|
Avalon® streaming | Supported in a future version of the SoC EDS. |
JTAG |