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1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
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7.1.1. HPS Reset Pin
You can configure this pin through Intel® Quartus® Prime Pro Edition.
Pin Function | Possible Settings | Functional Description |
---|---|---|
HPS cold nreset | SDM_IO0, SDM_IO10-16 | Assert this pin to trigger cold reset to the HPS. If the HPS is cold reset via software, this pin becomes an output pin and remain low until the HPS cold reset sequence is complete. |