Visible to Intel only — GUID: ebw1620226983312
Ixiasoft
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Agilex™ SoC FPGA Boot Flow
A. Document Revision History for Intel® Agilex™ SoC FPGA Boot User Guide
Visible to Intel only — GUID: ebw1620226983312
Ixiasoft
4.1. Overview
The configuration files are created by the Intel® Quartus® Prime Programming File Generator, using the following inputs:
- SOF file resulted from compilation of the hardware project in Intel® Quartus® Prime Software
- HPS First Stage Bootloader (FSBL) hex file resulted from compiling an HPS bootloader
- Intel® Quartus® Prime Firmware, which ends up running on the SDM
Figure 11. Overview of Configuration File Generation
The resulted configuration files contain the following components which are required for configuring the device:
Source | Component | Description |
---|---|---|
SOF File | HPS IO Configuration Data | Used for configuring HPS IOs including HPS DDR |
FPGA IO Configuration Data | Used for configuring FPGA IOs | |
FPGA Fabric Configuration Data | Used for configuring the FPGA fabric | |
Handoff Data for SDM Firmware | Used to pass parameters to SDM firmware | |
Handoff Data for HPS FSBL | Used to pass parameter to HPS FSBL | |
Intel® Quartus® Prime | SDM Firmware | Located at the beginning of configuration bitstream and can be executed as part of the configuration. |
Your HPS Software | HPS FSBL | First software ran on HPS after SDM takes it out of reset |