Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

48.2. Video Frame Writer IP Parameters

The IP offers compile-time parameters.
Table 929.  Video Frame Writer IP Parameters
Parameter Values Description
Video Data Format
Bits per color sample 8 to 16 Select the number of bits per color sample.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Maximum Frame Size
Maximum frame height 32 to 16384 Select the maximum height of frames. If you attempt to write fields or frames taller than this, they are cropped to this height.
Maximum frame width 32 to 16384

Select the maximum width of frames. If you attempt to write fields or frames wider than this, they are cropped to this width.

If you use the IP exclusively to write frames with 420 subsampling, optionally, halve the maximum frame width entry in the GUI. Halving the entry optimizes memory footprint because of the more efficient 420 pixel packing.

Control
Lite mode On or off Turn on to operate the frame writer in lite mode.
Separate clock for control interface On or off Turn on for a separate clock for the control interface.
Debug features On or off Turn on for debug features.
Memory
Avalon memory mapped host(s) local ports width 16, 32, 64, 128, 256, 512, 1024 Select in bits the width of the Avalon memory-mapped host write port. You must select a width at least as wide as the Intel streaming video input tdata width.
Avalon memory mapped host(s) local ports address width 8 to 32 Select in bits the width of the Avalon memory-mapped host write address port. It must be sufficient to fully address the last buffer.
The depth of the write FIFO 32,64,128,256,512,1024,2048 Specify the depth of the write FIFO buffer. Each FIFO buffer entry holds one word the width of the specified Avalon memory-mapped local port width. You must specify a FIFO depth of at least twice the specified burst target so that the IP can hold at least 2 bursts at any one time. Increase the FIFO depth to improve resilience to latency on the Avalon memory-mapped interface.
Avalon memory mapped write burst target 2,4,8,16,32,64 Select the burst target for writes. Longer bursts provide more efficiency on the bus but require more local storage in the write FIFO buffer.
Packing method Perfect, color or pixel Perfect packing minimizes memory footprint of stored frames but increases complexity and therefore size of the frame writer slightly. Color packing leaves spaces in memory between colors if colors do not pack into
Separate clock for the Avalon memory-mapped host interface(s) On or off
Figure 122. Frame Writer IP GUI