Visible to Intel only — GUID: pwl1620896321757
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. Adaptive Noise Reduction Intel® FPGA IP
11. Advanced Test Pattern Generator Intel® FPGA IP
12. AXI-Stream Broadcaster Intel® FPGA IP
13. Bits per Color Sample Adapter Intel FPGA IP
14. Black Level Correction Intel® FPGA IP
15. Black Level Statistics Intel® FPGA IP
16. Chroma Key Intel® FPGA IP
17. Chroma Resampler Intel® FPGA IP
18. Clipper Intel® FPGA IP
19. Clocked Video Input Intel® FPGA IP
20. Clocked Video to Full-Raster Converter Intel® FPGA IP
21. Clocked Video Output Intel® FPGA IP
22. Color Plane Manager Intel® FPGA IP
23. Color Space Converter Intel® FPGA IP
24. Defective Pixel Correction Intel® FPGA IP
25. Deinterlacer Intel® FPGA IP
26. Demosaic Intel® FPGA IP
27. FIR Filter Intel® FPGA IP
28. Frame Cleaner Intel® FPGA IP
29. Full-Raster to Clocked Video Converter Intel® FPGA IP
30. Full-Raster to Streaming Converter Intel® FPGA IP
31. Genlock Controller Intel® FPGA IP
32. Generic Crosspoint Intel® FPGA IP
33. Genlock Signal Router Intel® FPGA IP
34. Guard Bands Intel® FPGA IP
35. Histogram Statistics Intel® FPGA IP
36. Interlacer Intel® FPGA IP
37. Mixer Intel® FPGA IP
38. Pixels in Parallel Converter Intel® FPGA IP
39. Scaler Intel® FPGA IP
40. Stream Cleaner Intel® FPGA IP
41. Switch Intel® FPGA IP
42. Tone Mapping Operator Intel® FPGA IP
43. Test Pattern Generator Intel® FPGA IP
44. Unsharp Mask Intel® FPGA IP
45. Video and Vision Monitor Intel FPGA IP
46. Video Frame Buffer Intel® FPGA IP
47. Video Frame Reader Intel FPGA IP
48. Video Frame Writer Intel FPGA IP
49. Video Streaming FIFO Intel® FPGA IP
50. Video Timing Generator Intel® FPGA IP
51. Vignette Correction Intel® FPGA IP
52. Warp Intel® FPGA IP
53. White Balance Correction Intel® FPGA IP
54. White Balance Statistics Intel® FPGA IP
55. Design Security
56. Document Revision History for Video and Vision Processing Suite User Guide
31.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
31.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
31.4.3. Setting the VCXO hold over
31.4.4. Restarting the Genlock Controller IP
31.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
31.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
31.4.7. Disturbing a Reference Clock (a cable pull)
Visible to Intel only — GUID: pwl1620896321757
Ixiasoft
7.2. Protocol Converter IP Parameters
The IP offers compile-time parameters
Name | Values | Description |
---|---|---|
Bits per color sample | 8 to 16 | Number of bits that represent each color sample |
Number of color planes | 1 to 4 | Number of colors per pixel |
Number of pixels in parallel | 1 to 8 | Number of pixels transmitted per clock cycle. If either the input or output interface use the Avalon Streaming Video protocol, the number of pixels in parallel must be a power of two. |
YCbCr 444 color swap | On or off | Turn on to automatically correct for the color plane ordering differences between Avalon Streaming Video and Intel FPGA Streaming Video when transmitting YCbCr data with 4:4:4 chroma |
Control settings | ||
Memory-mapped control interface | On or off | Turn on to allow the Avalon memory-mapped control agent interface to update settings at run time |
Separate clock for control interface | On or off | Turn on for a separate clock domain for the Avalon memory-mapped control agent interface |
Debug features | On or off | Turn on for the debugging features of the Avalon memory-mapped control agent interface |
Pipeline Optimization | ||
Pipeline ready signals | On or off | Turn on to add extra pipeline registers to the AXI4-Stream or Avalon Streaming ready signals. Turning on this option may make it easier to close timing for the protocol converter and achieve a higher operation clock frequency, but may contribute to additional ALM usage. |
Interface Protocols | ||
Input protocol variant | Avalon Streaming Video, Intel FPGA Streaming Video Full, or Intel FPGA Streaming Video Lite | Select the protocol for the input interface |
Output protocol variant | Avalon Streaming Video, Intel FPGA Streaming Video Full, or Intel FPGA Streaming Video Lite | Select the protocol for the output interface |
Avalon Streaming Video Input Settings | ||
How Avalon-ST Video user packets are handled | No user packets expected at the input or Discard all user packets received | Select how the IP processes user packets if the input protocol is Avalon Streaming Video. If you do not expect the input stream to contain any user packets, you can select No user packets expected at the input and save the ALM resources required to discard these packets |
Video color space | RGB or YCbCr | If the input protocol is Avalon Streaming Video and you do not turn on Avalon memory-mapped control agent interface, you must specify the color space of the incoming video |
Video chroma sampling | 444, 422 or 420 | If the input protocol is Avalon Streaming Video and you turn off Avalon memory-mapped control agent interface, you must specify the chroma sampling of the incoming video |
Intel FPGA Streaming Video Lite input settings | ||
Enable low latency mode | On or off | If the input protocol is Intel FPGA Streaming Video this parameter determines the behavior of the Protocol Converter at the end of each video frame. |
Intel FPGA Streaming Video Full input settings | ||
How Intel FPGA Streaming Video aux packets are handled | Disable aux input, Discard all aux packets received, Pass all aux packets through to the output | Select how the IP processes auxiliary packets if the input protocol is Intel FPGA Streaming Video. |
Figure 12. Protocol Converter GUI