Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

32.2. Generic Crosspoint IP Parameters

The IP offers compile-time parameters.
Table 562.  Generic Crosspoint IP Parameters
Parameter Values Description
Control Settings
Memory-mapped control interface True or false Turn on for the memory-mapped control interface
Separate clock for control interface True or false

Turn on to run the run-time control interface on a different clock domain.

Crosspoint Settings
Crosspoint port width 1 to 1024 Width of crosspoint input and output ports in bits
Input (Per Input Interface)
Number of inputs 1 to 32 Number of crosspoint input ports
Conduit Signal type User-defined string Set the signal type of the input to match the type of the conduit it connects to.
Conduit associated clock True or false The conduit that the IP connects to may or may not have an associated clock set. This parameter sets the associated clock parameter of the input to main_clock.
Output (Per Output Interface)
Number of outputs 1 to 32 Number of crosspoint output ports
Default input 0 to 31 The output port selects this input by default out of reset. If run-time configuration is disabled, this setting is fixed.
Conduit Signal type User-defined string Set the signal type of the output to match the type of the conduit it connects to.
Conduit associated clock True or false The conduit that the IP connects to may or may not have an associated clock. This parameter sets the associated clock parameter of the output to main_clock