Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

22.3. Color Plane Manager IP Functional Description

You can select rearrange, split, or merge for the Color Plane Manager Mode.
Figure 54. Color Plane Manager Input and Outputs The figure shows input 0 and output 0 are always active and they receive and transmit Intel Streaming Video. The IP uses input 1 and output 1 depending on the Color Plane Manager Mode that you select.

When you select rearrange, you can set static padding values for any of the output 0 color planes. You can set these values statically at compile time (Color Plane Manager IP GUI - Rearrange Mode figure in Color Plane Manager Parameters shows the output color plane 3 has a static value of 77 decimal). Alternatively, you can turn on Memory mapped control interface in the GUI to change padding values on a per-frame basis at run time.

The IP passes Intel streaming video protocol metapackets from inputs to outputs with the video data. When you select Merge, if you want to propagate auxiliary and user metapackets from input 1 and input 0, turn on Keep input 1 aux/user metapackets in merge mode. When you select split, if you want to propagate auxiliary and user metapackets to output 1, turn on Keep input 1 aux/user metapackets in split mode.

Color Plane Examples with GUI Settings

Note: The figure show the IP starts numbering input and output color planes from 0, so an input or output with 4 color planes has planes 0,1,2 and 3.
Figure 55. Split Mode Example - extracting the luminance from a 2 color plane YCbCr input. If your system does not use output 1, it can use any output 1 settings as the IP synthesizes away any output 1 logic.
Table 343.  Parameters for Split Mode Example - extracting the luminance from a 2 color plane YCbCr input
Parameter Value
Number of color planes per pixel for input 0 2
Number of color plane per pixel for output 0 1
Split mode for output 0 Keep color plane 0
Figure 56. Split Mode Example – arbitrary selection of input color planes to outputs.
Table 344.  Parameters for Split Mode Example - arbitrary selection of input color planes to outputs
Parameter Value
Number of color planes per pixel for input 0 4
Number of color plane per pixel for output 0 2
Number of color plane per pixel for output 1 2
Split mode configuration for output 0

Keep color plane 1

Keep color plane 2

Split mode configuration for output 1

Keep color plane 0

Keep color plane 3

Figure 57. Split mode example – arbitrary selection of input color planes to outputs
Table 345.  Parameters for Split Mode Example - arbitrary selection of input color planes to outputs
Parameter Value
Number of color planes per pixel for input 0 4
Number of color plane per pixel for output 0 3
Number of color plane per pixel for output 1 2
Split mode configuration for output 0

Keep color plane 0

Keep color plane 2

Keep color plane 3

Split mode configurationfor output 1

Keep color plane 1

Keep color plane 3

Figure 58. Rearrange Mode Example: adding a configurable transparency alpha plane to a 3 color plane input to make a 4 color plane output
Table 346.  Parameters Rearrange Mode Example: adding a configurable transparency alpha plane to a 3 color plane input to make a 4 color plane output
Parameter Value
Number of color planes per pixel for input 0 3
Number of color plane per pixel for output 0 4
Mapping for output color plane 0 0
Mapping for output color plane 1 1
Mapping for output color plane 2 2
Mapping for output color plane 3 Padding
Static padding value for color plane 3 Required value or turn on Memory mapped control interface to set the alpha value at run time.
Figure 59. Rearrange Mode Example: mapping a 3 color plane RGB input to a 3 color plane BGR output
Table 347.  Parameters Rearrange Mode Example: mapping a 3 color plane RGB input to a 3 color plane BGR output
Parameter Value
Number of color planes per pixel for input 0 3
Number of color plane per pixel for output 0 3
Mapping for output color plane 0 2
Mapping for output color plane 1 1
Mapping for output color plane 2 0
Figure 60. Rearrange Mode Example: Extracting an alpha plane from a 4 color plane input to the low symbol of a 4 color plane output, with padding on upper 3 symbols
Table 348.  Parameters Rearrange Mode Example: extracting an alpha plane from a 4 color plane input to the low symbol of a 4 color plane output, with padding on upper 3 symbolsChanges to the padding values made via the run-time control register take effect on the next video line.
Parameter Value
Number of color planes per pixel for input 0 4
Number of color plane per pixel for output 0 4
Mapping for output color plane 0 3
Mapping for output color plane 1 Padding
Mapping for output color plane 2 Padding
Mapping for output color plane 3 Padding

Merge Description

When you select merge for Color Plane Manager Mode, the IP discards image information and end of field packets from input 1. The IP propagates auxiliary and user metapackets from input 1 if you turn on Keep IP1 aux/user metapackets in merge mode, otherwise the IP consumes them. The IP always propagates all metapackets from input 0. This behavior does not apply if you turn on Lite mode.

If video lines on the two inputs are of unequal length, the merged output is the shorter length and the remaining pixels of the longer line are consumed. Merging resumes with the next packet.

If video frames on the two inputs are of unequal height, the merged output has the same number of lines as the shorter frame and the IP consumes the extra lines on the other input. Merging resumes with the next start of frame.

If tvalid is low on one the inputs, the color plane manager IP lowers tready on its other input until both tvalid inputs are high. If tready is low on the color plane manager IP output, the color plane manager IP also lowers tready on both inputs until tready on the output is high.

Split Description

When you select split for Color Plane Manager Mode, the IP duplicates image information and end of field packets from input 0 to both outputs with video data packets. The IP always propagates auxiliary and user metapackets to output 0 and to output 1 if you turn on Keep OP1 aux/user metapackets in split mode . This behavior does not apply if you turn on Lite mode.

If one of the outputs experiences backpressure via tready, the color plane manager IP also lowers tready on its input until the tready signals on both outputs is high.

Rearrange Description

When you select rearrange for Color Plane Manager Mode, the IP transfers all metapackets and data packets to the output.

Register Behavior

Bit [0] of the csr_status register goes high when the IP starts producing the first frame. It goes low after the IP finishes producing the last line of the frame. It returns high when the IP starts producing the next frame.

Applications that need to know when the IP produces frames can poll this status register.

Latency

Table 349.  LatencyThe table shows the IP latency under ideal conditions.
Color Plane Manager Mode Latency (clock cycles)
Merge 15
Split 9
Rearrange 8

This latency increases if the streaming video outputs experience any backpressure via tready. Backpressure increases the latency by the same amount of cycles.

The padding values when you select merge do not change the latency.