Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

17.2. Chroma Resampler IP Parameters

The IP offers compile- and run-time parameters.
Parameter Value Description
Video data format
Lite mode On or off Turn on to use the Lite variant of the Intel FPGA Streaming Video protocol.
Bits per color sample 8 to 16 Select the number of bits per color sample.
Input pixels in parallel 1, 2, 4, 6, 8 Select the number of pixels transmitted every clock cycle at the input interface.
Output pixels in parallel 1, 2, 4, 6, 8 Select the number of pixels transmitted every clock cycle at the output interface.
Disable flush/fill between frames On or off Turn on to turn off the flush and refill of the line buffer between frames.
Maximum field width 1 to 16384 Set the maximum supported field width.
Chroma sampling support
4:2:0 passthrough On or off Turn on for passthrough of 4:2:0 chroma sampled fields.
4:2:0 to 4:2:2 conversion On or off Turn on for conversion from 4:2:0 chroma sampling at the input to 4:2:2 chroma sampling at the output.
4:2:0 to 4:4:4 conversion On or off Turn on for conversion from 4:2:0 chroma sampling at the input to 4:4:4 chroma sampling at the output.
4:2:2 passthrough On or off Turn on for passthrough of 4:2:2 chroma sampled fields.
4:2:2 to 4:2:0 conversion On or off Turn on for conversion from 4:2:2 chroma sampling at the input to 4:2:0 chroma sampling at the output.
4:2:2 to 4:4:4 conversion On or off Turn on for conversion from 4:2:2 chroma sampling at the input to 4:4:4 chroma sampling at the output.
4:4:4 passthrough On or off Turn on for passthrough of 4:4:4 chroma sampled fields.
4:4:4 to 4:2:0 conversion On or off Turn on for conversion from 4:4:4 chroma sampling at the input to 4:2:0 chroma sampling at the output.
4:4:4 to 4:2:2 conversion On or off Turn on for conversion from 4:4:4 chroma sampling at the input to 4:2:2 chroma sampling at the output.
Horizontal resampling settings
Horizontal resampling algorithm Nearest Neighbor, Bilinear, Filtered Select which resampling algorithm to use for all horizontal chroma resampling operations.
Horizontal chroma siting Left, Center Select the expected horizontal chroma siting for fields received at the input interface.
Horizontal luma adaptive resampling On or off Turn on for the luma adaptive algorithm for horizontal resampling conversions. Only if you select Filtered.
Vertical resampling settings
Vertical resampling algorithm Nearest Neighbor, Bilinear, Filtered Select which resampling algorithm to use for all vertical chroma resampling operations.
Vertical chroma siting Top, Center Select the expected vertical chroma siting for fields received at the input interface
Vertical luma adaptive resampling On or off Turn on for the luma adaptive algorithm for vertical resampling conversions. Only if you select Filtered.
Control settings
Memory-mapped control interface On or off Turn on to for the Avalon memory-mapped control agent interface and allow runtime configuration via the register map. You must have the Avalon memory-mapped control agent interface if you turn on Lite mode.
General
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-S tready signals.
Separate clock for control interface On or off Turn on for a separate clock for the control agent interface.
Debug features On or off Turn on to read back writeable registers via the control agent interface.