Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 7/08/2024
Public
Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. Adaptive Noise Reduction Intel® FPGA IP 11. Advanced Test Pattern Generator Intel® FPGA IP 12. AXI-Stream Broadcaster Intel® FPGA IP 13. Bits per Color Sample Adapter Intel FPGA IP 14. Black Level Correction Intel® FPGA IP 15. Black Level Statistics Intel® FPGA IP 16. Chroma Key Intel® FPGA IP 17. Chroma Resampler Intel® FPGA IP 18. Clipper Intel® FPGA IP 19. Clocked Video Input Intel® FPGA IP 20. Clocked Video to Full-Raster Converter Intel® FPGA IP 21. Clocked Video Output Intel® FPGA IP 22. Color Plane Manager Intel® FPGA IP 23. Color Space Converter Intel® FPGA IP 24. Defective Pixel Correction Intel® FPGA IP 25. Deinterlacer Intel® FPGA IP 26. Demosaic Intel® FPGA IP 27. FIR Filter Intel® FPGA IP 28. Frame Cleaner Intel® FPGA IP 29. Full-Raster to Clocked Video Converter Intel® FPGA IP 30. Full-Raster to Streaming Converter Intel® FPGA IP 31. Genlock Controller Intel® FPGA IP 32. Generic Crosspoint Intel® FPGA IP 33. Genlock Signal Router Intel® FPGA IP 34. Guard Bands Intel® FPGA IP 35. Histogram Statistics Intel® FPGA IP 36. Interlacer Intel® FPGA IP 37. Mixer Intel® FPGA IP 38. Pixels in Parallel Converter Intel® FPGA IP 39. Scaler Intel® FPGA IP 40. Stream Cleaner Intel® FPGA IP 41. Switch Intel® FPGA IP 42. Tone Mapping Operator Intel® FPGA IP 43. Test Pattern Generator Intel® FPGA IP 44. Unsharp Mask Intel® FPGA IP 45. Video and Vision Monitor Intel FPGA IP 46. Video Frame Buffer Intel® FPGA IP 47. Video Frame Reader Intel FPGA IP 48. Video Frame Writer Intel FPGA IP 49. Video Streaming FIFO Intel® FPGA IP 50. Video Timing Generator Intel® FPGA IP 51. Vignette Correction Intel® FPGA IP 52. Warp Intel® FPGA IP 53. White Balance Correction Intel® FPGA IP 54. White Balance Statistics Intel® FPGA IP 55. Design Security 56. Document Revision History for Video and Vision Processing Suite User Guide

8.2. 1D LUT IP Parameters

The IP offers run-time and compile-time parameters.
Parameter Values Description
Video Data Format
Lite mode On The IP only supports lite mode
Input bits per color sample 8 to 16 Select the number of input bits per color sample.
Output bits per color sample 8 to 16 Select the number of output bits per color sample.
Number of color planes 1 to 4 Number of color planes processed per pixel.
Number of pixels in parallel 1 to 8 Select the number of pixels in parallel.
Maximum Frame Size
Maximum field height 1k, 2k, 4k, 8k, 16k Specify the maximum height of incoming frames
Maximum field width 2k, 4k, 8k, 16k Specify the maximum width of incoming frames
Control Parameters
Equidistant LUT Entries On or off Turn on to distribute LUT entries equally across the dynamic range. When off, the IP divides the LUT into segments. When on, the segments at the lower end of the dynamic range are denser. The ones at the upper end are sparser.
Maximum number of bits to address all LUT entries 8 to 12 Maximum number of LUT entries in bits. This value cannot exceed the bits per color sample value.
Number of bits to address LUT segments Derived

When Equidistant LUT Entries is on, the IP divides the LUT into segments.

The IP derives this parameter from input bits per color sample, maximum number of LUT address bits, and sparsity bit parameters. Only visible when Equidistant LUT Entries is off.

Sparsity progression across segments (in bits) 1 to 2 The sparsity progression factor between neighboring LUT segments in number of address bits. Only available when Equidistant LUT Entries is off.
Reverse LUT On or off Allows you to use the LUT entries in reverse order.
General
Pipeline ready signal On or off Turn on to add extra pipeline registers to the AXI4-S tready signals
Separate clock for control interface On or off Turn on for a separate clock for the control agent interface
Debug features On or off Turn on to read back frame information registers and debugging information registers via the control agent interface.
Figure 13. 1D LUT IP GUI