Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel® FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel® FPGA IP 17. Pixels in Parallel Converter Intel® FPGA IP 18. Scaler Intel® FPGA IP 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel® FPGA IP 21. Video Frame Buffer Intel® FPGA IP 22. Video Streaming FIFO Intel® FPGA IP 23. Warp Intel® FPGA IP 24. Design Security 25. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Device Family Support 1.2. Video and Vision Processing IPs Release Information 1.3. Video and Vision Processing IPs Features 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. Chroma Resampler Intel® FPGA IP x
9.1. About the Chroma Resampler IP 9.2. Chroma Resampler IP Parameters 9.3. Chroma Resampler IP Functional Description 9.4. Chroma Resampler IP Registers 9.5. Chroma Resampler IP Software API
9.1. About the Chroma Resampler IP x
9.1.1. Chroma Resampler Performance and Resources
9.3. Chroma Resampler IP Functional Description x
9.3.1. Chroma Resampler IP Interfaces
10. Clipper Intel® FPGA IP x
10.1. About the Clipper IP 10.2. Clipper IP Parameters 10.3. Clipper IP Interfaces 10.4. Clipper IP Registers 10.5. Clipper IP Software API
10.1. About the Clipper IP x
10.1.1. Clipper IP Performance and Resources
11. Clocked Video to Full Raster Converter Intel® FPGA IP x
11.1. About the Clocked Video to Full Raster Converter IP 11.2. Clocked Video to Full Raster Converter Parameters 11.3. Clocked Video to Full Raster Converter Block Description 11.4. Clocked Video Converter to Full Raster IP Registers
11.1. About the Clocked Video to Full Raster Converter IP x
11.1.1. Clocked Video to Full Raster Converter Features 11.1.2. Clocked Video to Full Raster Converter Performance and Resources
11.3. Clocked Video to Full Raster Converter Block Description x
11.3.1. Clocked Video to Full Raster Converter Interfaces
12. Color Space Converter Intel® FPGA IP x
12.1. About the Color Space Converter IP 12.2. Color Space Converter IP Parameters 12.3. Color Space Converter IP Functional Description 12.4. Color Space Converter IP Registers 12.5. Color Space Converter IP Software API
12.1. About the Color Space Converter IP x
12.1.1. Color Space Converter IP Features 12.1.2. Color Space Converter IP Performance and Resources
12.3. Color Space Converter IP Functional Description x
12.3.1. Color Space Converter IP Interfaces
13. Full Raster to Clocked Video Converter Intel® FPGA IP x
13.1. About the Full Raster to Clocked Video Converter 13.2. Full Raster to Clocked Video Converter Parameters 13.3. Full Raster to Clocked Video Converter Block Description 13.4. Full Raster to Clocked Video Converter Registers
13.1. About the Full Raster to Clocked Video Converter x
13.1.1. Full Raster to Clocked Video Converter Features 13.1.2. Full Raster to Clocked Video Converter Performance and Resource Utilization
13.3. Full Raster to Clocked Video Converter Block Description x
13.3.1. Full Raster to Clocked Video Converter Interfaces
14. Full Raster to Streaming Converter Intel® FPGA IP x
14.1. About the Full Raster to Streaming Converter IP 14.2. Full Raster to Streaming Converter Parameters 14.3. Full Raster to Streaming Converter Block Description
14.1. About the Full Raster to Streaming Converter IP x
14.1.1. Full Raster to Streaming Converter Features 14.1.2. Full Raster to Streaming Converter Performance and Resources
14.3. Full Raster to Streaming Converter Block Description x
14.3.1. Full Raster to Streaming Converter Interfaces
15. Guard Bands Intel® FPGA IP x
15.1. About the Guard Bands IP 15.2. Guard Bands IP Parameters 15.3. Guard Bands IP Interfaces 15.4. Guard Bands IP Registers 15.5. Guard Bands IP Software API
15.1. About the Guard Bands IP x
15.1.1. Guard Bands IP Performance and Resources
16. Mixer Intel® FPGA IP x
16.1. About the Mixer IP 16.2. Mixer IP Parameters 16.3. Mixer IP Functional Description 16.4. Mixer IP Registers 16.5. Mixer IP Software API
16.1. About the Mixer IP x
16.1.1. Mixer IP Performance and Resources
16.3. Mixer IP Functional Description x
16.3.1. Mixer IP Interfaces
17. Pixels in Parallel Converter Intel® FPGA IP x
17.1. About the Pixels in Parallel Converter IP 17.2. Pixels in Parallel IP Converter Parameters 17.3. Pixels in Parallel Converter Interfaces 17.4. Pixels in Parallel Converter Registers 17.5. Pixels in Parallel Converter IP Software API
17.1. About the Pixels in Parallel Converter IP x
17.1.1. Pixels in Parallel IP Converter Performance and Resources
18. Scaler Intel® FPGA IP x
18.1. About the Scaler 18.2. Scaler IP Parameters 18.3. Scaler IP Functional Description 18.4. Scaler IP Registers 18.5. Scaler IP Software API
18.1. About the Scaler x
18.1.1. Scaler IP Performance and Resources
18.2. Scaler IP Parameters x
18.2.1. Updating Scaler IP Runtime Coefficients
18.3. Scaler IP Functional Description x
18.3.1. Scaler IP Interfaces
19. Tone Mapping Operator Intel® FPGA IP x
19.1. About the Tone Mapping Operator IP 19.2. TMO IP Parameters 19.3. TMO IP Block Description 19.4. TMO IP Registers 19.5. TMO IP Software API
19.1. About the Tone Mapping Operator IP x
19.1.1. TMO IP Features 19.1.2. TMO IP Performance and Resource Utilization
19.3. TMO IP Block Description x
19.3.1. TMO IP Interfaces 19.3.2. TMO IP Latency
20. Test Pattern Generator Intel® FPGA IP x
20.1. About the Test Pattern Generator IP 20.2. Test Pattern Generator IP Parameters 20.3. Test Pattern Generator IP Functional Description 20.4. Test Pattern Generator IP Registers 20.5. Test Pattern Generator IP Software API
20.1. About the Test Pattern Generator IP x
20.1.1. Test Pattern Generator IP Performance and Resources
20.3. Test Pattern Generator IP Functional Description x
20.3.1. Test Pattern Generator IP Interfaces
21. Video Frame Buffer Intel® FPGA IP x
21.1. About the Video Frame Buffer IP 21.2. Video Frame Buffer IP Parameters 21.3. Video Frame Buffer IP Functional Description 21.4. Video Frame Buffer IP Registers 21.5. Video Frame Buffer IP Software API
21.1. About the Video Frame Buffer IP x
21.1.1. Video Frame Buffer Performance and Resources
21.3. Video Frame Buffer IP Functional Description x
21.3.1. Video Frame Buffer IP Interfaces
22. Video Streaming FIFO Intel® FPGA IP x
22.1. About the Video Streaming FIFO IP 22.2. Video Streaming FIFO IP Parameters 22.3. Video Streaming FIFO IP Interfaces
22.1. About the Video Streaming FIFO IP x
22.1.1. Video Streaming FIFO IP Performance and Resources
23. Warp Intel® FPGA IP x
23.1. About the Warp IP 23.2. Warp IP Parameters 23.3. Warp IP Block Description 23.4. Warp IP Registers 23.5. Warp IP Software API
23.1. About the Warp IP x
23.1.1. Warp IP Features 23.1.2. Warp IP Performance and Resource Utilization
23.3. Warp IP Block Description x
23.3.1. Warp IP Interfaces 23.3.2. Warp IP Latency 23.3.3. External Memory for Warp IP
23.5. Warp IP Software API x
23.5.1. Using Warp IP Software 23.5.2. Warp IP Software Code Examples
24. Design Security x
24.1. Memory Subsystems 24.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide

18.4. Scaler IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 230.  Scaler IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_SCALER as appropriate and with an optional REG suffix
Address Register Access Description
Parameterization registers
0x0000 VID_PID RO

Read this register to retrieve scaler product ID.

This register always returns 0x6FA7_0234.

0x0004 VERSION RO

Read this register to retrieve the version information for the Intel Quartus release that Intel uses to build the scaler.

0x0008 LITE_MODE RO Read this register to determine if lite mode is on or off. This register returns 0 when you turn off lite and 1 when you turn on lite.
0x000C DEBUG_ENABLED RO Read this register to determine if debug features is on or off. This register returns 1 if reads to other registers designated as RW return the last value the IP writes to the register, or an undefined value.
0x0010 PIXELS_IN_PARALLEL RO Read this register to determine the number of pixels processed per clock cycle.
0x0014 MAX_INPUT_WIDTH RO Read this register to determine the maximum supported input field width.
0x0018 MAX_OUTPUT_WIDTH RO Read this register to determine the maximum supported output field width.
0x001C ALGORITHM RO Read this register to determine which algorithm the scaler is configured to use. Returns 0 for nearest neighbour, 1 for bilinear and 2 for polyphase.
0x0020 COEFFS_RUNTIME_LOAD RO Read this register to determine if updates to the coefficients at runtime via the Avalon memory-mapped agent interface are supported. Returns 1 if updates are supported and 0 otherwise.
0x0024 COEFF_MEM_INIT RO Read this register to determine if the scaler is configured with pre-initialised coefficients at reset. Returns 1 if the coefficients are preinitialised and 0 otherwise.
0x0028 V_SCALING_ENABLED RO Read this register to determine if the scaler is configured to support vertical scaling. Returns 1 if vertical scaling is supported and 0 otherwise.
0x002C V_NUM_TAPS RO Read this register to determine the number of vertical scaling filter taps.
0x0030 V_NUM_PHASES RO Read this register to determine the number of vertical scaling filter phases.
0x0034 V_NUM_BANKS RO Read this register to determine the number of vertical scaling filter coefficient banks.
0x0038 V_COEFFS_SIGNED RO Read this register to determine if the vertical scaling filter uses signed coefficients. Returns 1 is the coefficients are signed and 0 otherwise.
0x003C V_COEFFS_INT_BITS RO Read this register to determine the number of integer bits used to represent the vertical scaling filter coefficients.
0x0040 V_COEFFS_FRAC_BITS RO Read this register to determine the number of fraction bits that represent the vertical scaling filter coefficients.
0x0044 H_SCALING_ENABLED RO Read this register to determine if the scaler supports horizontal scaling. Returns 1 if horizontal scaling is supported and 0 otherwise.
0x0048 H_NUM_TAPS RO Read this register to determine the number of horizontal scaling filter taps.
0x004C H_NUM_PHASES RO Read this register to determine the number of horizontal scaling filter phases.
0x0050 H_NUM_BANKS RO Read this register to determine the number of horizontal scaling filter coefficient banks.
0x0054 H_COEFFS_SIGNED RO Read this register to determine if the horizontal scaling filter uses signed coefficients. Returns 1 is the coefficients are signed and 0 otherwise.
0x0058 H_COEFFS_INT_BITS RO Read this register to determine the number of integer bits to represent the horizontal scaling filter coefficients.
0x005C H_COEFFS_FRAC_BITS RO Read this register to determine the number of fraction bits to represent the horizontal scaling filter coefficients.
0x0060 to 0x011F - - Unused.
Table 231.  Scaler IP Control and Debug RegistersFor more information, refer to Control Packets. In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_SCALER as appropriate and with an optional REG suffix
Address Register Access Description
Lite 45 Full
0x0120 IMG_INFO_WIDTH RW RO

When you turn on lite, use this register to set the expected width of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the width that the scaler derives from information in the image information packet.

0x0124 IMG_INFO_HEIGHT RW RO

When you turn on lite, use this register to set the expected height of incoming video fields.

When you turn off lite and turn on Debug features, this register returns the height that the scaler derives from information in the image information packet.

0x0128 IMG_INFO_INTERLACE - RO When you turn off lite and turn on Debug features, this register returns the interlace nibble that the scaler derives from information in the image information packet. Unused in lite mode.
0x012C Reserved - - Reserved
0x0130 IMG_INFO_COLORSPACE - RO When you turn off lite and turn on Debug features, this register returns the color space that the scaler derives from information in the image information packet. Unused in lite mode.
0x0134 IMG_INFO_SUBSAMPLING - RO When you turn off lite and turn on Debug features, this register returns the subsampling that the scaler derives from information in the image information packet. Unused in lite mode.
0x0138 IMG_INFO_COSITING - RO When you turn off lite and turn on Debug features, this register returns the cositing that the scaler derives from information in the image information packet. Unused in lite mode.
0x013C IMG_INFO_FIELD_COUNT - RO When you turn off lite and turn on Debug features, this register returns the field count that the scaler derives from information in the image information packet. Unused in lite mode.
0x012C to 0x013C - - - Unused.
0x0140 STATUS RO

Bit 0 : Status bit.

1 means scaler is processing a video field, 0 otherwise.

When you turn off lite:

Bit 1 : Pending register updates bit.

Any writes to the settings register (0x0148 - 0x0154) cause the IP to raise pending register updates bit, to indicate outstanding changes to the clipping settings.

The IP lowers this bit at the next field boundary after a write to the COMMIT register.

0x0144 COMMIT RW Only use when you turn off lite. The IP holds any changes to the scaling settings (not coefficients) via the register map until you issue a write to this register. The value you write is unimportant.
0x0148 OUTPUT_WIDTH RW Write to this register to set the output field width. Unused if horizontal scaling is not enabled
0x014C OUTPUT_HEIGHT RW Write to this register to set the output field height. Unused if vertical scaling is not enabled
0x0150 H_BANK RW Write to this register to set the read bank for the horizontal scaling filter coefficients.
0x0154 V_BANK RW Write to this register to set the read bank for the vertical scaling filter coefficients
0x0158 to 0x01FC - - Unused.
0x0200 RT_COEFF_LOAD_BANK_SELECT WO Write to this register to set the index of the scaling filter coefficient bank that is being updated
0x0204 RT_COEFF_LOAD_PHASE_SELECT WO Write to this register to set the index of the scaling filter phase that you are updating
0x0208 RT_COEFF_LOAD_COMMIT WO Write 1 to this register to commit the coefficient information in the RT_COEFF_LOAD_TAP_X registers to the horizontal scaling filter coefficient bank and phase specified in RT_COEFF_LOAD_BANK_SELECT and RT_COEFF_LOAD_PHASE_SELECT respectively. Write 0 to this register to commit the coefficient information in the RT_COEFF_LOAD_TAP_X registers to the vertical scaling filter coefficient bank and phase specified in RT_COEFF_LOAD_BANK_SELECT and RT_COEFF_LOAD_PHASE_SELECT respectively.
0x020C-0x0308 RT_COEFF_LOAD_TAP_0 - RT_COEFF_LOAD_TAP_63 WO Up to 64 registers to set the new coefficient values for a vertical or horizontal scaling filter phase. If the vertical scaling filter has N taps, only the first N registers need to update before writing to the RT_COEFF_LOAD_COMMIT register. If the horizontal scaling filter has M taps, only the first M registers need to update before writing to the RT_COEFF_LOAD_COMMIT register.

Register Bit Descriptions

Table 232.  VID_PID
Name Bits Description
Scaler version ID and product ID 31:0 This register always returns 0x0000_0234.
  • 15:0 is the product ID and always returns 0x0234
  • 31:16 is the vendor ID and always returns 0x6AF7
Table 233.  VERSION
Name Bits Description
Lite mode parameterization bit 7:0 Register map version. This returns 0x01.
QPDS patch revision 15:8 Returns 0x00 .
QPDS update revision 23:16 Updated for each release. For 214, returns 0x04 .
QPDS major revision 31:24 Updated for each release. For 21.4, returns 0x15.
Table 234.  LITE_MODE
Name Bits Description
Lite mode parameterization bit 31:0 Returns 1 if lite mode is on and 0 otherwise.
Table 235.  DEBUG_ENABLED
Name Bits Description
Debug features parameterization bit 31:0 Returns 1 if debug features is on and 0 otherwise.
Table 236.  PIXELS_IN_PARALLEL
Name Bits Description
Pixels in parallel 31:0 Number of pixels processed per clock cycle.
Table 237.  MAX_INPUT_WIDTH
Name Bits Description
Maximum input width 31:0 Maximum supported input field width.
Table 238.  MAX_OUTPUT_WIDTH
Name Bits Description
Maximum output width 31:0 Maximum supported output field width.
Table 239.  ALGORITHM
Name Bits Description
Algorithm 31:0 Returns 0 for nearest neighbour, 1 for bilinear and 2 for polyphase.
Table 240.   COEFFS_RUNTIME_LOAD
Name Bits Description
Runtime load 31:0 Returns 1 if Runtime coefficient updates is on and 0 otherwise. Only valid for polyphase.
Table 241.   COEFF_MEM_INIT
Name Bits Description
Coefficient memory initialised 31:0 Returns 1 if the scaling filter coefficient memory is preinitialised at reset and 0 otherwise. Only valid for polyphase.
Table 242.   V_SCALING_ENABLED
Name Bits Description
Vertical scaling enabled 31:0 Returns 1 if Enable vertical scaling is on and 0 otherwise
Table 243.   V_NUM_TAPS
Name Bits Description
Vertical scaling filter taps 31:0 Returns the number of vertical scaling filter taps.
Table 244.   V_NUM_PHASES
Name Bits Description
Vertical scaling filter phases 31:0 Returns the number of vertical scaling filter phases. Only valid for polyphase.
Table 245.   V_NUM_BANKS
Name Bits Description
Vertical scaling filter coefficient banks 31:0 Returns the number of vertical scaling filter coefficient banks. Only valid if polyphase scaling is selected.
Table 246.   V_COEFFS_SIGNED
Name Bits Description
Vertical scaling filter coefficients signed 31:0 Returns 1 if the vertical scaling filter coefficients are signed values and 0 otherwise. Only valid for polyphase.
Table 247.   V_COEFFS_INT_BITS
Name Bits Description
Vertical scaling filter coefficients integer bits 31:0 Returns the number of integer bits used to represent the vertical scaling filter coefficients. Only valid for polyphase.
Table 248.   V_COEFFS_FRAC_BITS
Name Bits Description
Vertical scaling filter coefficients fraction bits 31:0 Returns the number of fraction bits to represent the vertical scaling filter coefficients. Only valid for polyphase.
Table 249.   H_SCALING_ENABLED
Name Bits Description
Horizontal scaling enabled 31:0 Returns 1 if horizontal scaling is enabled and 0 otherwise.
Table 250.  H_NUM_TAPS
Name Bits Description
Horizontal scaling filter taps 31:0 Returns the number of horizontal scaling filter taps.
Table 251.   H_NUM_PHASES
Name Bits Description
Horizontal scaling filter phases 31:0 Returns the number of horizontal scaling filter phases. Only valid for polyphase.
Table 252.   H_NUM_BANKS
Name Bits Description
Horizontal scaling filter coefficient banks 31:0 Returns the number of horizontal scaling filter coefficient banks. Only valid for polyphase.
Table 253.   H_COEFFS_SIGNED
Name Bits Description
Horizontal scaling filter coefficients signed 31:0 Returns 1 if the horizontal scaling filter coefficients are signed values and 0 otherwise. Only valid for polyphase.
Table 254.   H_COEFFS_INT_BITS
Name Bits Description
Horizontal scaling filter coefficients integer bits 31:0 Returns the number of integer bits to represent the horizontal scaling filter coefficients. Only valid for polyphase.
Table 255.   H_COEFFS_FRAC_BITS
Name Bits Description
Horizontal scaling filter coefficients fraction bits 31:0 Returns the number of fraction bits to represent the horizontal scaling filter coefficients. Only valid for polyphase.
Table 256.   IMG_INFO_WIDTH
Name Bits Description
Width bits 15:0

When lite mode is on, write to this register to set the expected width of the incoming video fields.

For full parameterizations with debug features enabled, this register returns the width-1 field from the most recently received image information packet and adds 1 to return a value for width.

unused 31:16 Unused.
Table 257.   IMG_INFO_HEIGHT
Name Bits Description
Height bits 15:0

When lite mode is on, write to this register to set the expected height of the incoming video fields.

For full parameterizations with debug features enabled, this register reads the height-1 field from the most recently received image information packet and adds 1 to return a value for height.

unused 31:16 Unused.
Table 258.  IMG_INFO_INTERLACE
Name Bits Description
IntlaceNibble bits 3:0

When lite mode is on, this register has no function.

When lite mode is off with debug features on, this register returns the intlaceNibble field from the most recently received image information packet .

unused 31:4 Unused.
Table 259.  IMG_INFO_COLORSPACE
Name Bits Description
CSP code bits 6:0

When lite mode is on, this register has no function.

When lite mode is off with debug features on, this register returns the 7 bit CSP field from the most recently received image information packet .

unused 31:7 Unused.
Table 260.  IMG_INFO_SUBSAMPLING
Name Bits Description
SubSa code bits 1:0

When lite mode is on, this register has no function.

When lite mode is off with debug features on, this register returns the SUBSA field from the most recently received image information packet.

unused 31:2 Unused.
Table 261.  IMG_INFO_COSITING
Name Bits Description
Cosite code bits 1:0

When lite mode is on, this register has no function.

When lite mode is off with debug features on,, this register returns the COSITE field from the most recently received image information packet.

unused 31:2 Unused.
Table 262.  IMG_INFO_FIELD_COUNT
Name Bits Description
Count bits 6:0

When lite mode is on, this register has no function.

When lite mode is off with debug features on,, this register returns the 7 bit FIELD_COUNT field from the most recently received image information packet.

unused 31:7 Unused.
Table 263.  STATUS
Name Bits Description
Status bit 0 1 means scaler is processing a video field, 0 otherwise.
Pending register updates bit 1 1 means scaler has pending updates, 0 otherwise
unused 31:2 Unused.
Table 264.  COMMIT
Name Bits Description
unused 31:0 Unused.
Table 265.  OUTPUT_WIDTH
Name Bits Description
Output width 15:0 Output field width
unused 31:16 Unused.
Table 266.  OUTPUT_HEIGHT
Name Bits Description
Output height 15:0 Output field height
unused 31:16 Unused.
Table 267.  H_BANK
Name Bits Description
Horizontal scaling filter coefficient read bank 3:0 Horizontal scaling filter coefficient read bank.
unused 31:4 Unused.
Table 268.  V_BANK
Name Bits Description
Vertical scaling filter coefficient read bank 3:0 Vertical scaling filter coefficient read bank.
unused 31:4 Unused.
Table 269.  RT_COEFF_LOAD_BANK_SELECT
Name Bits Description
Coefficient write bank 3:0 Index of coefficient bank to be updated
unused 31:4 Unused.
Table 270.  RT_COEFF_LOAD_PHASE_SELECT
Name Bits Description
Coefficient write phase 7:0 Index of coefficient phase to be updated
unused 31:8 Unused.
Table 271.  RT_COEFF_LOAD_COMMIT
Name Bits Description
unused 31:0 Unused.
Table 272.  RT_COEFF_LOAD_TAP_X
Name Bits Description
Coefficient value coeff_width-1:0 Coefficient value for filter tap X
unused 31:coeff_width Unused.
45

When you turn on lite mode, registers are RW only if you turn on Debug features, otherwise they are WO. For full, turn off lite mode.

Level Two Title