Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel® FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel® FPGA IP 17. Pixels in Parallel Converter Intel® FPGA IP 18. Scaler Intel® FPGA IP 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel® FPGA IP 21. Video Frame Buffer Intel® FPGA IP 22. Video Streaming FIFO Intel® FPGA IP 23. Warp Intel® FPGA IP 24. Design Security 25. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Device Family Support 1.2. Video and Vision Processing IPs Release Information 1.3. Video and Vision Processing IPs Features 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. Chroma Resampler Intel® FPGA IP x
9.1. About the Chroma Resampler IP 9.2. Chroma Resampler IP Parameters 9.3. Chroma Resampler IP Functional Description 9.4. Chroma Resampler IP Registers 9.5. Chroma Resampler IP Software API
9.1. About the Chroma Resampler IP x
9.1.1. Chroma Resampler Performance and Resources
9.3. Chroma Resampler IP Functional Description x
9.3.1. Chroma Resampler IP Interfaces
10. Clipper Intel® FPGA IP x
10.1. About the Clipper IP 10.2. Clipper IP Parameters 10.3. Clipper IP Interfaces 10.4. Clipper IP Registers 10.5. Clipper IP Software API
10.1. About the Clipper IP x
10.1.1. Clipper IP Performance and Resources
11. Clocked Video to Full Raster Converter Intel® FPGA IP x
11.1. About the Clocked Video to Full Raster Converter IP 11.2. Clocked Video to Full Raster Converter Parameters 11.3. Clocked Video to Full Raster Converter Block Description 11.4. Clocked Video Converter to Full Raster IP Registers
11.1. About the Clocked Video to Full Raster Converter IP x
11.1.1. Clocked Video to Full Raster Converter Features 11.1.2. Clocked Video to Full Raster Converter Performance and Resources
11.3. Clocked Video to Full Raster Converter Block Description x
11.3.1. Clocked Video to Full Raster Converter Interfaces
12. Color Space Converter Intel® FPGA IP x
12.1. About the Color Space Converter IP 12.2. Color Space Converter IP Parameters 12.3. Color Space Converter IP Functional Description 12.4. Color Space Converter IP Registers 12.5. Color Space Converter IP Software API
12.1. About the Color Space Converter IP x
12.1.1. Color Space Converter IP Features 12.1.2. Color Space Converter IP Performance and Resources
12.3. Color Space Converter IP Functional Description x
12.3.1. Color Space Converter IP Interfaces
13. Full Raster to Clocked Video Converter Intel® FPGA IP x
13.1. About the Full Raster to Clocked Video Converter 13.2. Full Raster to Clocked Video Converter Parameters 13.3. Full Raster to Clocked Video Converter Block Description 13.4. Full Raster to Clocked Video Converter Registers
13.1. About the Full Raster to Clocked Video Converter x
13.1.1. Full Raster to Clocked Video Converter Features 13.1.2. Full Raster to Clocked Video Converter Performance and Resource Utilization
13.3. Full Raster to Clocked Video Converter Block Description x
13.3.1. Full Raster to Clocked Video Converter Interfaces
14. Full Raster to Streaming Converter Intel® FPGA IP x
14.1. About the Full Raster to Streaming Converter IP 14.2. Full Raster to Streaming Converter Parameters 14.3. Full Raster to Streaming Converter Block Description
14.1. About the Full Raster to Streaming Converter IP x
14.1.1. Full Raster to Streaming Converter Features 14.1.2. Full Raster to Streaming Converter Performance and Resources
14.3. Full Raster to Streaming Converter Block Description x
14.3.1. Full Raster to Streaming Converter Interfaces
15. Guard Bands Intel® FPGA IP x
15.1. About the Guard Bands IP 15.2. Guard Bands IP Parameters 15.3. Guard Bands IP Interfaces 15.4. Guard Bands IP Registers 15.5. Guard Bands IP Software API
15.1. About the Guard Bands IP x
15.1.1. Guard Bands IP Performance and Resources
16. Mixer Intel® FPGA IP x
16.1. About the Mixer IP 16.2. Mixer IP Parameters 16.3. Mixer IP Functional Description 16.4. Mixer IP Registers 16.5. Mixer IP Software API
16.1. About the Mixer IP x
16.1.1. Mixer IP Performance and Resources
16.3. Mixer IP Functional Description x
16.3.1. Mixer IP Interfaces
17. Pixels in Parallel Converter Intel® FPGA IP x
17.1. About the Pixels in Parallel Converter IP 17.2. Pixels in Parallel IP Converter Parameters 17.3. Pixels in Parallel Converter Interfaces 17.4. Pixels in Parallel Converter Registers 17.5. Pixels in Parallel Converter IP Software API
17.1. About the Pixels in Parallel Converter IP x
17.1.1. Pixels in Parallel IP Converter Performance and Resources
18. Scaler Intel® FPGA IP x
18.1. About the Scaler 18.2. Scaler IP Parameters 18.3. Scaler IP Functional Description 18.4. Scaler IP Registers 18.5. Scaler IP Software API
18.1. About the Scaler x
18.1.1. Scaler IP Performance and Resources
18.2. Scaler IP Parameters x
18.2.1. Updating Scaler IP Runtime Coefficients
18.3. Scaler IP Functional Description x
18.3.1. Scaler IP Interfaces
19. Tone Mapping Operator Intel® FPGA IP x
19.1. About the Tone Mapping Operator IP 19.2. TMO IP Parameters 19.3. TMO IP Block Description 19.4. TMO IP Registers 19.5. TMO IP Software API
19.1. About the Tone Mapping Operator IP x
19.1.1. TMO IP Features 19.1.2. TMO IP Performance and Resource Utilization
19.3. TMO IP Block Description x
19.3.1. TMO IP Interfaces 19.3.2. TMO IP Latency
20. Test Pattern Generator Intel® FPGA IP x
20.1. About the Test Pattern Generator IP 20.2. Test Pattern Generator IP Parameters 20.3. Test Pattern Generator IP Functional Description 20.4. Test Pattern Generator IP Registers 20.5. Test Pattern Generator IP Software API
20.1. About the Test Pattern Generator IP x
20.1.1. Test Pattern Generator IP Performance and Resources
20.3. Test Pattern Generator IP Functional Description x
20.3.1. Test Pattern Generator IP Interfaces
21. Video Frame Buffer Intel® FPGA IP x
21.1. About the Video Frame Buffer IP 21.2. Video Frame Buffer IP Parameters 21.3. Video Frame Buffer IP Functional Description 21.4. Video Frame Buffer IP Registers 21.5. Video Frame Buffer IP Software API
21.1. About the Video Frame Buffer IP x
21.1.1. Video Frame Buffer Performance and Resources
21.3. Video Frame Buffer IP Functional Description x
21.3.1. Video Frame Buffer IP Interfaces
22. Video Streaming FIFO Intel® FPGA IP x
22.1. About the Video Streaming FIFO IP 22.2. Video Streaming FIFO IP Parameters 22.3. Video Streaming FIFO IP Interfaces
22.1. About the Video Streaming FIFO IP x
22.1.1. Video Streaming FIFO IP Performance and Resources
23. Warp Intel® FPGA IP x
23.1. About the Warp IP 23.2. Warp IP Parameters 23.3. Warp IP Block Description 23.4. Warp IP Registers 23.5. Warp IP Software API
23.1. About the Warp IP x
23.1.1. Warp IP Features 23.1.2. Warp IP Performance and Resource Utilization
23.3. Warp IP Block Description x
23.3.1. Warp IP Interfaces 23.3.2. Warp IP Latency 23.3.3. External Memory for Warp IP
23.5. Warp IP Software API x
23.5.1. Using Warp IP Software 23.5.2. Warp IP Software Code Examples
24. Design Security x
24.1. Memory Subsystems 24.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide

9.5. Chroma Resampler IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_crs_regs.h

Include file: intel_vvp_crs.h

Table 75.  Chroma Resampler IP API reference
Name Description
intel_vvp_crs_init Initialize the Chroma Resampler instance
intel_vvp_core_* Accessors defined in Video and Vision Processing IPs Software Programming Model. Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_crs_get_lite_mode Returns if Lite Mode is on.
intel_vvp_crs_get_debug_enabled Returns if Debug features is on.
intel_vvp_crs_is_conversion_supported Returns if the IP supports a specified chroma resampling.
intel_vvp_crs_is_running Returns if the IP is currently processing video data.
intel_vvp_crs_get_commit_status Returns uncommitted writes.
intel_vvp_crs_get_status Reads the status register.
intel_vvp_crs_set_output_subsampling Selects the current output subsampling.
intel_vvp_crs_get_output_subsampling Returns the current selected output subsampling.
intel_vvp_crs_commit_writes Commit all outstanding writes.

enum eIntelCrsSubsampling

Members

kIntelVvpCrsSubsampling420 (0) – 4:2:0 subsampling, chroma planes resolution is halved vertically and horizontally

kIntelVvpCrsSubsampling422 (2) – 4:2:2 subsampling, chroma planes resolution is halved horizontally

kIntelVvpCrsSubsampling444 (3) – 4:4:4 subsampling, chroma planes are fully sampled

kIntelVvpCrsSubsamplingInvalid (1) – Invalid subsampling (used to indicate errors)

Description

Enumeration for the supported chroma subsamplings

intel_vvp_crs_init

Prototype 
int intel_vvp_crs_init(intel_vvp_crs_instance *instance, intel_vvp_core_base base);
Description

Initializes a Chroma Resampler instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance will not be fully initialized and should not be used further by the application if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the Chroma Resamplerproduct ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpCrsRegMapVersionErr if the register map is not supported

intel_vvp_crs_get_lite_mode

Prototype 
bool intel_vvp_crs_get_lite_mode(intel_vvp_crs_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_crs_instance fully initialized

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_crs_get_debug_enabled

Prototype 
bool intel_vvp_crs_get_debug_enabled(intel_vvp_crs_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_crs_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_crs_is_conversion_supported

Prototype 
 bool intel_vvp_crs_is_conversion_supported (intel_vvp_crs_instance *instance, eIntelCrsSubsampling input_subsampling, eIntelCrsSubsampling output_subsampling);
Description

Returns the value of the MAX_WIDTH register. The instance must be a valid intel_vvp_crs_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

input_subsampling – the input subsampling

output_subsampling – the output subsampling

Returns

if chroma resampling, or pass-through, from the input subsampling to the output subsampling is supported

intel_vvp_crs_is_running

Prototype 
bool intel_vvp_crs_is_running(intel_vvp_crs_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_crs_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

True is the IP is currently receiving/storing an input field, false when between two input fields

intel_vvp_crs_get_commit_status

Prototype 
bool intel_vvp_crs_get_commit_status(intel_vvp_clipper_instance* instance);
Description

Reads and returns the commit pending bit of the STATUS register. The instance must be a valid intel_vvp_crs_instance fully initialized and configured in full mode.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

True is the IP is configured in full mode and if the agent interface contains uncommitted writes.

intel_vvp_crs_get_status

Prototype 
uint32_t intel_vvp_crs_get_status(intel_vvp_crs_instance* instance);
Description

Reads the STATUS register. The instance must be a valid intel_vvp_crs_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

The content of the STATUS register

intel_vvp_crs_set_output_subsampling

Prototype 
int intel_vvp_crs_set_output_subsampling(intel_vvp_crs_instance* instance, eIntelCrsSubsampling output_subsampling);
Description

Selects the required output subsampling. Use intel_vvp_core_set img_info_subsampling to set the input subsampling in lite mode. The instance must be a valid intel_vvp_crs_instance fully initialized. The call does not check if the IP supports the requested chroma resampling conversion and a default conversion will be used if the input/output selections are unsupported.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

output_subsampling – requested output subsampling

Returns

kIntelVvpCoreOk or a negative error code in case of error

kIntelVvpCoreInstanceErr, if the instance is the NULL pointer

kIntelVvpCrsParamErr, if one, or both, subsampling is/are invalid

intel_vvp_crs_get_output_subsampling

Prototype

eIntelCrsSubsampling intel_vvp_crs_get_output_subsampling(intel_vvp_crs_instance* instance);

Description

Reads the OUTPUT_SUBSAMPLING register. The instance must be a valid intel_vvp_crs_instance fully initialized and configured in debug mode.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

the last value written to the OUTPUT_SUBSAMPLING register or kIntelVvpCrsSubsamplingInvalid in case of errors

intel_vvp_crs_commit_writes

Prototype 
int intel_vvp_crs_commit_writes(intel_vvp_crs_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid and parameterized in full mode.

Arguments

instance – pointer to the intel_vvp_crs_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

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