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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide
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3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
Intel offers IPs to convert between the two protocols. This topic compares the differences of control and data packets from the Avalon Streaming Video protocol to metapackets and video packets from the Intel Streaming Video Protocol.
Control and Image Information Packets
Figure 7. Control Packets for Both ProtocolsThe Avalon streaming video protocol has a ready latency of 1. The figure shows a transition a to b where the first valid cycle of the packet occurs in cycle 2, one clock cycle after the sink raises its ready. The Intel FPGA streaming video protocol has a ready latency of 0.
The Avalon streaming video protocol indicates control packets with the value 0xf in the low nibble of the first beat of the transaction. The control packet payload is then packed over subsequent beats into the low nibbles of each byte, across the whole width of the data bus. The Intel FPGA streaming video protocol indicates image information packets by setting tuser[1] and 0x0 in the low 5 bits of the first beat. The protocol uses the remaining 11 bits of the first beat and the low 16 bits of subsequent beats to pack the remainder of the image informaiton control packet.
Avalon streaming video carries data for the width field of the control packets in 4 nibbles spread across multiple bytes and often over multiple beats on the bus (w3:w0 in the figure). The Intel FPGA streaming video protocol always contains the 16 width field bits in the second beat of the transaction (w3:w0 in cycle 3 in the figure). Both protocols process the height field in these ways.
Interlace nibble codes have the same semantics in both protocols. Avalon streaming video carries interface nibble codes in the low nibble of the last byte of the packet. Intel FPGA streaming video packs them in positions 8 down to 5 of the first beat of the packet.
The Avalon streaming video protocol makes use of the Avalon streaming empty signal to indicate any empty symbols in the last beat. The Intel FPGA streaming video protocol does not use the AXI4-Stream TKEEP or TSRB signals.
Data packets
Data packets in the Avalon streaming video protocol represent one entire field or frame of video. The Intel FPGA streaming video protocol transports each line of video as individual data packet. Data packets are also ready latency 1 in the Avalon streaming video protocol.
The protocols have other differences for pixel packing and empty symbols. The protocol converter IP manages these differences, so you do not need to understand the difference between the two standards.