Video and Vision Processing Suite Intel® FPGA IP User Guide

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Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel® FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel® FPGA IP 17. Pixels in Parallel Converter Intel® FPGA IP 18. Scaler Intel® FPGA IP 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel® FPGA IP 21. Video Frame Buffer Intel® FPGA IP 22. Video Streaming FIFO Intel® FPGA IP 23. Warp Intel® FPGA IP 24. Design Security 25. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Device Family Support 1.2. Video and Vision Processing IPs Release Information 1.3. Video and Vision Processing IPs Features 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. Chroma Resampler Intel® FPGA IP x
9.1. About the Chroma Resampler IP 9.2. Chroma Resampler IP Parameters 9.3. Chroma Resampler IP Functional Description 9.4. Chroma Resampler IP Registers 9.5. Chroma Resampler IP Software API
9.1. About the Chroma Resampler IP x
9.1.1. Chroma Resampler Performance and Resources
9.3. Chroma Resampler IP Functional Description x
9.3.1. Chroma Resampler IP Interfaces
10. Clipper Intel® FPGA IP x
10.1. About the Clipper IP 10.2. Clipper IP Parameters 10.3. Clipper IP Interfaces 10.4. Clipper IP Registers 10.5. Clipper IP Software API
10.1. About the Clipper IP x
10.1.1. Clipper IP Performance and Resources
11. Clocked Video to Full Raster Converter Intel® FPGA IP x
11.1. About the Clocked Video to Full Raster Converter IP 11.2. Clocked Video to Full Raster Converter Parameters 11.3. Clocked Video to Full Raster Converter Block Description 11.4. Clocked Video Converter to Full Raster IP Registers
11.1. About the Clocked Video to Full Raster Converter IP x
11.1.1. Clocked Video to Full Raster Converter Features 11.1.2. Clocked Video to Full Raster Converter Performance and Resources
11.3. Clocked Video to Full Raster Converter Block Description x
11.3.1. Clocked Video to Full Raster Converter Interfaces
12. Color Space Converter Intel® FPGA IP x
12.1. About the Color Space Converter IP 12.2. Color Space Converter IP Parameters 12.3. Color Space Converter IP Functional Description 12.4. Color Space Converter IP Registers 12.5. Color Space Converter IP Software API
12.1. About the Color Space Converter IP x
12.1.1. Color Space Converter IP Features 12.1.2. Color Space Converter IP Performance and Resources
12.3. Color Space Converter IP Functional Description x
12.3.1. Color Space Converter IP Interfaces
13. Full Raster to Clocked Video Converter Intel® FPGA IP x
13.1. About the Full Raster to Clocked Video Converter 13.2. Full Raster to Clocked Video Converter Parameters 13.3. Full Raster to Clocked Video Converter Block Description 13.4. Full Raster to Clocked Video Converter Registers
13.1. About the Full Raster to Clocked Video Converter x
13.1.1. Full Raster to Clocked Video Converter Features 13.1.2. Full Raster to Clocked Video Converter Performance and Resource Utilization
13.3. Full Raster to Clocked Video Converter Block Description x
13.3.1. Full Raster to Clocked Video Converter Interfaces
14. Full Raster to Streaming Converter Intel® FPGA IP x
14.1. About the Full Raster to Streaming Converter IP 14.2. Full Raster to Streaming Converter Parameters 14.3. Full Raster to Streaming Converter Block Description
14.1. About the Full Raster to Streaming Converter IP x
14.1.1. Full Raster to Streaming Converter Features 14.1.2. Full Raster to Streaming Converter Performance and Resources
14.3. Full Raster to Streaming Converter Block Description x
14.3.1. Full Raster to Streaming Converter Interfaces
15. Guard Bands Intel® FPGA IP x
15.1. About the Guard Bands IP 15.2. Guard Bands IP Parameters 15.3. Guard Bands IP Interfaces 15.4. Guard Bands IP Registers 15.5. Guard Bands IP Software API
15.1. About the Guard Bands IP x
15.1.1. Guard Bands IP Performance and Resources
16. Mixer Intel® FPGA IP x
16.1. About the Mixer IP 16.2. Mixer IP Parameters 16.3. Mixer IP Functional Description 16.4. Mixer IP Registers 16.5. Mixer IP Software API
16.1. About the Mixer IP x
16.1.1. Mixer IP Performance and Resources
16.3. Mixer IP Functional Description x
16.3.1. Mixer IP Interfaces
17. Pixels in Parallel Converter Intel® FPGA IP x
17.1. About the Pixels in Parallel Converter IP 17.2. Pixels in Parallel IP Converter Parameters 17.3. Pixels in Parallel Converter Interfaces 17.4. Pixels in Parallel Converter Registers 17.5. Pixels in Parallel Converter IP Software API
17.1. About the Pixels in Parallel Converter IP x
17.1.1. Pixels in Parallel IP Converter Performance and Resources
18. Scaler Intel® FPGA IP x
18.1. About the Scaler 18.2. Scaler IP Parameters 18.3. Scaler IP Functional Description 18.4. Scaler IP Registers 18.5. Scaler IP Software API
18.1. About the Scaler x
18.1.1. Scaler IP Performance and Resources
18.2. Scaler IP Parameters x
18.2.1. Updating Scaler IP Runtime Coefficients
18.3. Scaler IP Functional Description x
18.3.1. Scaler IP Interfaces
19. Tone Mapping Operator Intel® FPGA IP x
19.1. About the Tone Mapping Operator IP 19.2. TMO IP Parameters 19.3. TMO IP Block Description 19.4. TMO IP Registers 19.5. TMO IP Software API
19.1. About the Tone Mapping Operator IP x
19.1.1. TMO IP Features 19.1.2. TMO IP Performance and Resource Utilization
19.3. TMO IP Block Description x
19.3.1. TMO IP Interfaces 19.3.2. TMO IP Latency
20. Test Pattern Generator Intel® FPGA IP x
20.1. About the Test Pattern Generator IP 20.2. Test Pattern Generator IP Parameters 20.3. Test Pattern Generator IP Functional Description 20.4. Test Pattern Generator IP Registers 20.5. Test Pattern Generator IP Software API
20.1. About the Test Pattern Generator IP x
20.1.1. Test Pattern Generator IP Performance and Resources
20.3. Test Pattern Generator IP Functional Description x
20.3.1. Test Pattern Generator IP Interfaces
21. Video Frame Buffer Intel® FPGA IP x
21.1. About the Video Frame Buffer IP 21.2. Video Frame Buffer IP Parameters 21.3. Video Frame Buffer IP Functional Description 21.4. Video Frame Buffer IP Registers 21.5. Video Frame Buffer IP Software API
21.1. About the Video Frame Buffer IP x
21.1.1. Video Frame Buffer Performance and Resources
21.3. Video Frame Buffer IP Functional Description x
21.3.1. Video Frame Buffer IP Interfaces
22. Video Streaming FIFO Intel® FPGA IP x
22.1. About the Video Streaming FIFO IP 22.2. Video Streaming FIFO IP Parameters 22.3. Video Streaming FIFO IP Interfaces
22.1. About the Video Streaming FIFO IP x
22.1.1. Video Streaming FIFO IP Performance and Resources
23. Warp Intel® FPGA IP x
23.1. About the Warp IP 23.2. Warp IP Parameters 23.3. Warp IP Block Description 23.4. Warp IP Registers 23.5. Warp IP Software API
23.1. About the Warp IP x
23.1.1. Warp IP Features 23.1.2. Warp IP Performance and Resource Utilization
23.3. Warp IP Block Description x
23.3.1. Warp IP Interfaces 23.3.2. Warp IP Latency 23.3.3. External Memory for Warp IP
23.5. Warp IP Software API x
23.5.1. Using Warp IP Software 23.5.2. Warp IP Software Code Examples
24. Design Security x
24.1. Memory Subsystems 24.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide

13.3.1. Full Raster to Clocked Video Converter Interfaces

The IP has three functional interfaces:
  • Full raster data input interface for video IOs
  • Intel clocked video data output interface for video IOs
  • Avalon memory-mapped CPU interface
Table 150.   Clocks and Resets
Name Direction Width Description
vid_clock Input 1

When you select Lite and CVI, this is the video clock for the lite and clocked video outputs, and the streaming full raster input.

When you select CVO, the clocked video outputs bus can contain an optional input clock. If you turn on the clocked video output input clock, this signal is a dummy signal retained for Platform Designer connectivity. The IP uses the video clock included in the cv_vid_out conduit.

vid_reset Input 1 Reset for vid_clock domain.
cpu_clock Input 1 Optional control interface clock.
cpu_reset Input 1 Optional control interface reset.
cv_clk_out Output 1 A copy of the video clock that the IP uses.
Table 151.  Control InterfaceThis interface is only available if you select True for Memory mapped control interface.
Name Direction Width Description
av_mm_cpu_agent_address Input 7 Control agent port Avalon memory-mapped address bus. Specifies a word offset into the slave address space..
av_mm_cpu_agent_read Input 1 Control agent port Avalon memory-mapped read signal. When you assert this signal, the control port drives new data onto the read data bus.
av_mm_cpu_agent_readdata Output 32 Control agent port Avalon memory-mapped read data bus. These output lines are used for read transfers.
av_mm_cpu_agent_waitrequest Output 1 Control agent port Avalon memory-mapped wait request bus. This signal indicates that the slave is stalling the host transaction.
av_mm_cpu_agent_write Input 1 Control agent port Avalon memory-mapped write signal. When you assert this signal, the control port accepts new data from the write data bus.
av_mm_cpu_agent_writedata Input 32 Control agent port Avalon memory-mapped write data bus. These input lines are used for writing transfers.
av_mm_cpu_agent_byteenable Input 4 Control agent port Avalon memory-mapped byte enable bus. These lines indicate which bytes are selected for write and read transactions..
Table 152.  Intel FPGA streaming full raster video interface
Name Direction Width Description
axi4s_fr_vid_in_tvalid Input 1 AXI4-S full raster data valid.
axi4s_fr_vid_in_tready Output 1 Optional AXI4-S full raster data ready.
axi4s_fr_vid_in_tdata Input 24 AXI4-S full raster data in.
axi4s_fr_vid_in_tlast Input 1 AXI4-S end of full raster packet.
axi4s_fr_vid_in_tuser[0] Input 25 AXI4-S start of full raster video frame.
Table 153.   CV Lite Streaming Video Interface This interface is only available if you select Lite for CV Bus Style.
Name Direction Width Description
cv_vid_out_h Output Pixels in parallel When asserted, the video is in a horizontal blanking.
cv_vid_out_v Output Pixels in parallel When asserted, the video is in a vertical blanking.
cv_vid_out_h_sync Output Pixels in parallel When asserted, the video is in a horizontal synchronization period.
cv_vid_out_v_sync Output Pixels in parallel When asserted, the video is in a vertical synchronization period..
cv_vid_out_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_active Output Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking). You must drive this signal for correct operation of the IPs.
cv_vid_out_data Output 26 Pixel data
cv_vid_out_valid Output 1 When asserted, the output is valid.
cv_vid_out_ready Input 1 When asserted, the IP can drive new data. When deasserted, the IP can drive no new data.
Table 154.   Clocked Video Input Streaming Video Interface This interface is only available if you select CVI for CV Bus Style.
Name Direction Width Description
cv_vid_out_vid_clk Input 1 The pixel synchronous clock.
cv_vid_out_vid_h_sync Output Pixels in parallel When asserted, the video is in a horizontal blanking or synchronization period.
cv_vid_out_vid_v_sync Output Pixels in parallel When asserted, the video is in a vertical blanking or synchronization period.
cv_vid_out_vid_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_vid_data Output 27 Pixel data.
cv_vid_out_vid_de Output Pixels in parallel When asserted, the video is in an active picture period (not horizontal or vertical blanking).
cv_vid_out_vid_datavalid Output 1 When asserted, the output is valid.
cv_vid_out_vid_locked Output 1 Unused legacy signal.
cv_vid_out_vid_hd_sdn Output 1 Unused legacy signal.
cv_vid_out_vid_std Output User Specified Unused legacy signal.
cv_vid_out_vid_color_encoding Output 8 Unused legacy signal.
cv_vid_out_vid_bit_width Output 8 Unused legacy signal.
cv_vid_out_vid_total_sample_width Output 16 Indicates the total (active + blanking) width of the raster.
cv_vid_out_vid_total_line_count Output 16 Indicates the total (active + blanking) height of the raster.
cv_vid_out_vid_hdmi_duplication Output 4 Unused legacy signal.
cv_vid_out_sof Input 1 Unused legacy signal.
cv_vid_out_sof_locked Input 1 Unused legacy signal.
cv_vid_out_refclk_div Input 1 Unused legacy signal.
cv_vid_out_clipping Input 1 Unused legacy signal.
cv_vid_out_padding Input 1 Unused legacy signal.
cv_vid_out_overflow Input 1 Unused legacy signal.
Table 155.  Clocked Video Output Streaming Video InterfaceThis interface is only available if you select CVO for CV Bus Style.
Name Direction Width Description
cv_vid_out_vid_clk Input 1 Pixel synchronous clock.
cv_vid_out_vid_h Output Pixels in parallel When asserted, the video is in a horizontal blanking.
cv_vid_out_vid_v Output Pixels in parallel When asserted, the video is in a vertical blanking.
cv_vid_out_vid_h_sync Output Pixels in parallel When asserted, the video is in a horizontal synchronization period.
cv_vid_out_vid_v_sync Output Pixels in parallel When asserted, the video is in a vertical synchronization period.
cv_vid_out_vid_f Output Pixels in parallel When asserted, the video is interlaced and in field 1. When deasserted, the video is either progressive or interlaced and in field 0.
cv_vid_out_vid_data Output 28 Pixel data.
cv_vid_out_vid_datavalid Output Pixels in parallel When asserted, the output is valid.
cv_vid_out_underflow Output 1 Unused legacy signal.
cv_vid_out_vid_mode_change Output 1 Unused legacy signal.
cv_vid_out_vid_vcoclk_div Output 1 Unused legacy signal.
cv_vid_out_vid_sof_locked Output 1 Unused legacy signal.
cv_vid_out_vid_sof Output 1 Unused legacy signal.
cv_vid_out_vid_std Output 6 Unused legacy signal.
Related Information
24

The equation gives the sizes of all tdata widths in these interfaces;

max (floor(((bits per color sample x (number of color planes+1) x pixels in parallel) + 7) / 8) x 8, 16)

25

The equation gives the sizes of all tuser widths in these interfaces

N = ceil (tdata width / 8)

26

The equation gives the data width size:

width = (bits per color sample X number of color planes X pixels in parallel)

27

The equation gives the data width size:

width = (bits per color sample X number of color planes X pixels in parallel)

28

The equation gives the data width sizes:

width = (bits per color sample X number of color planes X pixels in parallel)

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