Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
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Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.10. Performing Reconfiguration with the System Console Tool

With the Avalon to JTAG Master Bridge, reconfiguration commands are directly streamed to the Reconfiguration Controller through the JTAG port. The System Console tool issues commands to initiate dynamic reconfiguration of the Native PHY IP.

This design example uses a Tcl script called main.tcl that consists of several different procedures with different functionality.

Note: Program the Arria V GX device with the SOF generated in the previous section before launching the System Console. Having both the programmer and System Console open simultaneously can cause programming errors.

Before any reconfiguration can take place, you must first launch the System Console tool. To launch the System Console, perform the following steps:

  1. Program the Arria V Device with the SOF generated from the original design
  2. Launch the Quartus II software
  3. From the Quartus II software, on the Tools menu, click Qsys
  4. From the Qsys tool, on the Tools menu, click System Console
  5. Ensure that the present working directory contains main.tcl

The following table lists the procedures in main.tcl. You can type in a procedure name and its value to execute the reconfiguration process. Verify your results with the signal tap file (stp1.stp) by looking at the signals listed in the following table.

Table 5.  Description of Procedures in main.tcl

Command Name

<Value>

Description

txpll_register <Value>

0

Select logical TX PLL 0 as TX PLL (fPLL). Only the tx_std_clkout frequency is updated.

1

Select logical TX PLL 1 as TX PLL (CMU PLL). Only the tx_std_clkout frequency is updated.

txpll_mif <Value>

2500

Select logical TX PLL 0 as TX PLL (fPLL). Both the tx_std_clkout and rx_std_clkout frequencies are updated.

5000

Select logical TX PLL 1 as TX PLL (CMU PLL). Both the tx_std_clkout and rx_std_clkout frequencies are updated.

reset

N/A

System Reset

sloopback <Value>

1

Enable serial loopback. Verify with the rx_seriallpbken port in the signal tap file

0

Disable serial loopback. Verify with the rx_seriallpbken port in the signal tap file

read_vod

N/A

Read back VOD value (read back data in hexadecimal value)

write_vod <Value>

0-63

Writing VOD value with valid settings of 0-63

patternalign <Value>

1

Enable pattern alignment detection. To resynchronize to the new word boundary after each MIF based reconfiguration, use this command to create a 0-to-1 transition to the rx_std_wa_patternalign signal.

0

Disable pattern alignment detection. Set this signal to 0 to re-assert the rx_std_wa_patternalign signal.

To reconfigure the transceiver channel, type the reconfiguration commands as shown below in the Tcl Console. For example: 

source main.tcl

sloopback 1
>> Enable serial loopback

txpll_mif 2500
>> TX PLL switch to fPLL. Data channel at 2500 Mbps 

reset
>> Reset the transceiver channel after each streamer-based 
>> reconfiguration
		
txpll_mif 5000
>> TX PLL switch to CMU PLL. Data channel at 5000 Mbps

reset
>> Reset the transceiver channel after each streamer-based 
>> reconfiguration

These commands allow the System Console to communicate directly with the Avalon to JTAG Bridge Master, which in turn communicates with the Reconfiguration Controller.

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