Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
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Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.3. Creating the Reconfiguration Controller

The Reconfiguration Controller controls the dynamic reconfiguration of Arria V and Cyclone V PHY IPs.

The following steps describe how to set up the Reconfiguration Controller to dynamically control the PMA settings, change the PLL selection by streaming a MIF, and trigger DCD calibration manually.

The Native PHY IP created in the previous section requires two reconfiguration interfaces, one for the REGULAR RX/TX Channel and one for the CDR TX PLL, as shown in the following figure. You can verify the logical interface information in the Transceiver Reconfiguration Report.

Figure 5. Transceiver Reconfiguration Report
Transceiver Reconfiguration Report

The Transceiver Reconfiguration Report is located under Fitter Report > GXB Report.

Refer to the parameters setting in the figure below to set up the Interface Bundles, Transceiver Calibration functions, Analog Features, and Reconfiguration Features functions.

Figure 6. Arria V Transceiver Reconfiguration Controller


The Interface Bundles section specifies two interface bundles. The first interface is connected to the RX/TX channels as shown in Figure 5. The second interface is connected to the CMU PLL.

The following table shows the Interface Bundles connection in the top-level design file a5_top.v.

Table 2.  Interface Bundles Parameters

Reconfiguration Ports

Native PHY/ CMU PLL Ports

Connected to

[69:0] ch0_0_to_xcvr

[45:0] ch0_0_from_xcvr

[69:0] reconfig_to_xcvr

[45:0] reconfig_from_xcvr

Connected to RX/TX channel

[69:0] ch1_1_to_xcvr

[45:0] ch1_1_from_xcvr

[69:0] reconfig_to_cmu

[45:0] reconfig_from_cmu

Connected to CMU PLL

In the Transceiver Calibration Functions section, turn on the Enable duty cycle calibration option.

In the Analog Features section, turn on the Enable Analog controls option to enable VOD setting reconfiguration.

In the Reconfiguration Features section, turn on the Enable channel/PLL reconfiguration option to allow the streamer-based reconfiguration process. This reconfiguration mode reconfigures the TX/RX data path, CDR settings, and TX PLL selection.

After all parameters have been specified, you can generate the Reconfiguration Controller.

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