Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
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Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration

You can trigger the DCD calibration IP manually.

The following table lists the steps to access the reconfiguration address reserved for DCD calibration IP. You must trigger the DCD calibration IP when you switch from 2500 Mbps to 5000 Mbps because it switches the clock network and the channel data rate is >4915.2 Mbps. In the design example, the DCD calibration is triggered when the data channel is running at 5000 Mbps and after TX PLL switching happens. You can refer to the txpll_mif procedure in main.tcl for more details.

Table 7.  Using the Register-Based Reconfiguration Method to Trigger DCD Calibration

Step

Reconfiguration Step

Memory Map Address

Value Written

Description

1

Write to the logical channel register

0x48

0h

Logical channel 0 selected (Physical ch0)

2

Write to the data offset register

0x4B

0h

Select DCD calibration mode

3

Write 1 to manually trigger ON DCD calibration IP

0x4C

1h

Manually turn ON DCD calibration IP

4

Check reconfig_busy signals

Port

N/A

reconfig_busy signal stays asserted as long as the DCD IP is calibrating the TX buffer.

5

Write 0 to manually trigger OFF DCD calibration IP

0x4C

0h

Manually turn OFF DCD calibration IP

Note: Reset your channel after each manual DCD calibration.
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