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1.4.1. Creating the Qsys System
1.4.2. Creating the Transceiver Native PHY IP
1.4.3. Creating the Reconfiguration Controller
1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL
1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL
1.4.6. Creating the Transceiver PHY Reset Controller
1.4.7. Creating a ROM that Contains the MIF for Reconfiguration
1.4.8. Compiling the Design Example
1.4.9. Creating In-System Sources and Probes (ISSP)
1.4.10. Performing Reconfiguration with the System Console Tool
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1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL
The design example uses the Arria V Transceiver PLL to clock the transceiver channel at 5000 Mbps.
When you turn on the Use external TX PLL option in the Native PHY IP, you can connect to this external transceiver PLL. This transceiver PLL is referring to the CMU PLL as illustrated in the System Diagram. You can instantiate this IP in the MegaWizard™ Plug-in Manager > Interface > Transceiver PHY > Arria V Transceiver PLL v12.1.
Refer to the following figure to set the parameters for the CMU PLL.
Figure 7. Arria V Transceiver PLL Parameters Setting When Configured as CMU PLL
You do not have to turn on the Enable PLL reconfiguration option if you are not dynamically reconfiguring the PLL parameter settings. This option allows you to change the PLL settings to support different data rates.
Note: If you are using an fPLL in your design, if you want to switch the fPLL with another CMU PLL, you must instantiate the CMU PLL using the Arria V Transceiver PLL IP. Turn on the option Use external TX PLL in the Native PHY IP to instantiate a CMU PLL.