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1.4.1. Creating the Qsys System
1.4.2. Creating the Transceiver Native PHY IP
1.4.3. Creating the Reconfiguration Controller
1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL
1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL
1.4.6. Creating the Transceiver PHY Reset Controller
1.4.7. Creating a ROM that Contains the MIF for Reconfiguration
1.4.8. Compiling the Design Example
1.4.9. Creating In-System Sources and Probes (ISSP)
1.4.10. Performing Reconfiguration with the System Console Tool
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1.4.1. Creating the Qsys System
The reconfiguration design example uses a simple Qsys system that consists of three components: the JTAG to Avalon Master Bridge, the External Slave Interface, and the PIO.
Follow the steps below to examine the Qsys system:
- Launch the Quartus II software
- On the File menu, click Open
- Browse and select the console_interface.qsys file located in the original_design/ directory
- Click Open