Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

Download PDF
ID 683321
Date 12/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.8. Compiling the Design Example

The compilation process generates an .sof programming file for the Arria V device.

At this point in the procedure, two designs exist: the original design and the MIF design.

The MIF design is compiled first because the MIF generated will be used by the original design. Specifically, the MIF generated by the MIF design is used in the original design to configure from one data rate to another. To compile a design:

  1. Open the MIF project in the Quartus II software.
  2. On the Processing menu, click Start Compilation.

The changes you make in the MIF design are the Native PHY IP parameters listed in the "MIFs Generation in Reference with Native PHY IP Settings" table. Generate a 5000 Mbps design by setting the parameters in your Native PHY IP to create a mif_5000.mif file. Next, generate a 2500 Mbps design by setting the parameters in your Native PHY IP to create a mif_2500.mif file.

Note: If you get an error message related to a missing .mif (before the MIF is generated and specified in the ROM MegaWizard Plug-In Manager), select the "No, leave it blank" option at the Memory Initialization tab of the MegaWizard Plug-In Manager.

After a successful compilation, a reconfig_mif directory is created in the MIF design’s project directory. The following MIFs are used for each data rate:

  • 2500 Mbps – mif_2500.mif
  • 5000 Mbps – mif_5000.mif

The original design is compiled after the MIF design. However, before the original design is compiled, you must specify the MIF created by the MIF design. The module mif_rom is used to store the MIF. Follow the steps below to specify the MIF.

  1. Open the original project in the Quartus II software.
  2. Launch the MegaWizard Plug-In Manager from the Tools menu.
  3. From the MegaWizard, browse to the original_design/ directory and select mif_rom.v.
  4. All parameters are the same except that you must specify the MIF. Specify the mif_design/reconfig_mif/mif_2500.mif file by browsing to the MIF.
  5. Click Finish to generate the new mif_rom module.
  6. Repeat these steps for the ROM to store the MIF for 5000 Mbps.

After the MIF has been specified, the original design is ready to be compiled. Follow the steps below to compile the design.

  1. Open the original project in the Quartus II software.
  2. On the Processing menu, click Start Compilation.

After a successful compilation, a file named a5_top.sof will exist in the original/output_files/ directory. This SOF is used to program the Arria V GX device.

Note: There is only one .qar project in this design example. Use this .qar project as both the original design and the MIF design to generate the MIF files. To create the MIF design, duplicate the original design.
Related Information
Level Two Title