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1.4.1. Creating the Qsys System
1.4.2. Creating the Transceiver Native PHY IP
1.4.3. Creating the Reconfiguration Controller
1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL
1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL
1.4.6. Creating the Transceiver PHY Reset Controller
1.4.7. Creating a ROM that Contains the MIF for Reconfiguration
1.4.8. Compiling the Design Example
1.4.9. Creating In-System Sources and Probes (ISSP)
1.4.10. Performing Reconfiguration with the System Console Tool
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1.6. Document Revision History
Date | Version | Changes |
---|---|---|
December 2015 | 2015.12.04 | Updated URLs for links in several sections. |
March 2015 | 2015.03.04 | Corrected the "Value Written" entry in step 5 of the "Using the Register-Based Reconfiguration Method to Trigger DCD Calibration" table. |
April 2014 | 2014.04.01 | Added a link to the reference design example in the "Arria V GX Dynamic Reconfiguration Design Example" section. |
January 2014 | 2014.01.21 |
|
October 2013 | 2013.10.11 | Updated the "Using the Register-Based Reconfiguration Method to Reconfigure VOD Settings" table. |
April 2013 | 2013.04.11 |
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March 2013 | 2013.03.01 | Initial release. |