Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

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ID 683321
Date 12/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices x
1.1. Reconfiguration Methods 1.2. Transceiver Calibration Function 1.3. Unsupported Reconfiguration Modes 1.4. Arria V GX Dynamic Reconfiguration Design Example 1.5. Duty Cycle Distortion Calibration 1.6. Document Revision History
1.1. Reconfiguration Methods x
1.1.1. Register-Based Reconfiguration 1.1.2. Streamer-Based Reconfiguration
1.4. Arria V GX Dynamic Reconfiguration Design Example x
1.4.1. Creating the Qsys System 1.4.2. Creating the Transceiver Native PHY IP 1.4.3. Creating the Reconfiguration Controller 1.4.4. Creating the CMU PLL Using an Arria V Transceiver PLL 1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL 1.4.6. Creating the Transceiver PHY Reset Controller 1.4.7. Creating a ROM that Contains the MIF for Reconfiguration 1.4.8. Compiling the Design Example 1.4.9. Creating In-System Sources and Probes (ISSP) 1.4.10. Performing Reconfiguration with the System Console Tool
1.4.1. Creating the Qsys System x
1.4.1.1. The Qsys System Components
1.4.10. Performing Reconfiguration with the System Console Tool x
1.4.10.1. Streaming a MIF to Perform Channel Reconfiguration 1.4.10.2. Manual Trigger for DCD Calibration IP via Register-based Reconfiguration 1.4.10.3. Performing VOD Reconfiguration via Register-Based Reconfiguration
1. Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in Arria V and Cyclone V Devices

1.4.5. Creating a Fractional PLL (fPLL) using Altera PLL

The design example uses the Altera PLL v12.1 to configure an fPLL to clock the transceiver channel at 2500 Mbps.

To connect the Native PHY IP to the fPLL, you must turn on the Use external TX PLL option in the Native PHY IP. You can instantiate this IP in the MegaWizard Plug-in Manager > IO > Altera PLL v12. Refer to the figure below to set the parameters in the fPLL.

Figure 8. Altera PLL Parameters Setting when Configured as an fPLL
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