Visible to Intel only — GUID: nik1412634868437
Ixiasoft
Visible to Intel only — GUID: nik1412634868437
Ixiasoft
1.4.6. Creating the Transceiver PHY Reset Controller
The design example uses the Transceiver PHY Reset Controller to control the reset sequence of the transceiver channel.
As shown in the figure below, set the Number of TX PLLs field to 2. In this design example, you switch the TX PLL between the CMU PLL and fPLL. Therefore, you must connect both PLL locked signals, pll_locked[1:0], to the reset controller to indicate the release of tx_digitalreset. The reset controller releases tx_digitalreset whenever there is an assertion on either of the pll_locked[1:0] signals. Leave the remaining settings in the PHY Reset Controller to their default values.