Visible to Intel only — GUID: hco1410462461200
Ixiasoft
Visible to Intel only — GUID: hco1410462461200
Ixiasoft
4.3.2. Transceiver and Clocking
The device’s Gigabit transceivers operate at 5.4, 2.7, and 1.62 Gbps, and require a 135-MHz single reference clock. When the link rate changes, the state machine only reconfigures the transceiver PLL settings.
Parameters |
Single Reference Clock Settings |
---|---|
Datapath Options |
|
Enable TX datapath | On |
Enable RX datapath | On |
Enable standard PCS | On |
Number of data channels | 1, 2 or 4 |
Note: If you select 1 or 2, you must instantiate the PHY instance multiple times for all data channels as per maximum lane count parameter. These values are for non-bonded mode.
|
|
Bonding mode | ×1* or ×N |
Note: If you select ×1, you must instantiate the PHY instance multiple times for all data channels as per maximum lane count parameter. This value is for non-bonded mode.
|
|
Enable simplified data interface | |
PMA |
|
Data rate | 1620 Mbps (when TX maximum link rate = 1.62 Gbps) 2700 Mbps (when TX maximum link rate = 2.7 Gbps) 5400 Mbps (when TX maximum link rate = 5.4 Gbps) |
TX local clock division factor | 1 |
TX PMA |
|
Enable TX PLL dynamic reconfiguration | On |
Number of TX PLLs | 1 |
Main TX PLL logical index | 0 |
Number of TX PLL reference clock | 1 |
TX PLL0 |
|
PLL type | CMU |
Reference clock frequency | 135 MHz |
Selected reference clock source | 0 |
Selected clock network | ×1 or ×N |
Note: If you select ×1, you must instantiate the PHY instance multiple times for all data channels as per maximum lane count parameter. This value is for non-bonded mode.
|
|
RX PMA |
|
Enable CDR dynamic reconfiguration | On |
Number of CDR reference clocks | 1 |
Selected CDR reference clock | 0 |
Selected CDR reference clock frequency | 135 MHz |
PPM detector threshold | 1000 ppm |
Enable rx_is_lockedtodata port | On |
Enable rx_is_lockedtoref port | On |
Enable rx_set_locktodata and rx_set_locktoref ports | On |
Standard PCS |
|
Standard PCS protocol mode | Basic |
Standard PCS/PMA interface width | 20 |
Byte Serializer and Deserializer |
|
Enable TX byte serializer | Off (when symbol output mode is Dual) On (when symbol output mode is Quad) |
Enable RX byte deserializer | Off (when symbol output mode is Dual) On (when symbol output mode is Quad) |