Visible to Intel only — GUID: hco1410462358618
Ixiasoft
Visible to Intel only — GUID: hco1410462358618
Ixiasoft
5.8.7. Secondary Stream Interface
The core calculates the associated parity bytes. The secondary stream interface uses the start-of-packet (SOP) and end-of-packet (EOP) to determine if the current input is a header or payload.
The ready latency is 1 clock cycle for the payload sub-packets. When core is ready, it sends the header forward. When the header is forwarded, the 16-byte payload (DB0 … DB15 and DB16 … DB31) must be available and the core must assert its associated valid signal on the next clock cycle when the output ready signal is high. The valid signal must remain low until the ready signal is high.
The core supports only 16-byte and 32-byte payloads. Payloads that contain only the first 16 data bytes can assert the EOP on the second valid pulse to terminate the packet sequence. The core clocks in the data to the secondary stream interface through tx_ss_clk. tx_ss_clk is at the same phase and frequency as the main link lane 0 clock.
You can also use the secondary stream data packet to transport HDR metadata. CTA-861-G specification defines the HDR InfoFrame packet information as Packet Type, Version, data packets, and so on. The HDR metadata must follow InfoFrame SDP version 1.3 format defined in the VESA DisplayPort Standard version 1.4a.
For example, if the CTA-861-G specification-defined HDR InfoFrame type is 0x07, the VESA DisplayPort Standard version 1.4a-defined SDP InfoFrame Header Byte 1 as secondary-data packet type is 80h + Non-audio InfoFrame type value. The Header Byte 1 (HB1 in Figure 23) must be written to 87h.