DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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Document Table of Contents

11.9.26. DPRX_AUX_HPD

HPD control.

Address: 0x0119

Direction: RW

Reset: 0x00000000

Table 201.  DPRX_AUX_HPD Bits

Bit

Bit Name

Function

31:13

Unused

12

HPD_IRQ

Writing this bit at 1 generates a 0.75-ms long HPD IRQ (low pulse). This bit is WO.

To use this bit, HPD_EN must be 1.

11

HPD_EN

HPD logic level

0 = Deasserted (low)

1 = Asserted (high)

10:0

Unused