IP Core Information |
Core Features |
- Conforms to the Video Electronics Standards Association (VESA) DisplayPort Standard version 2.0
- Scalable main data link
- 1, 2, or 4 lane operation
- 1.62, 2.7, 5.4, 8.1, and 10.0 gigabits per second (Gbps) per lane with an embedded clock 1 2
- Color support
- RGB 18, 24, 30, 36, or 48 bpp
- YCbCr 4:4:4 24, 30, 36, or 48 bpp
- YCbCr 4:2:2 16, 20, 24, or 32 bpp
- YCbCr 4:2:0 12, 15, 18, or 24 bpp
- 8B/10B Channel Coding supports 40-bit (quad symbol) and 20-bit (dual symbol) transceiver data interface
- 128B/132B Channel Coding supports 32-bit transceiver data interface
- Support for 1, 2, or 4 parallel pixels per clock
- Support for 2 or 8 audio channels
- 8B/10B Channel Coding supports Multi-stream transport (MST)
- Intel® Arria® 10 devices support up to 4 streams
- Intel® Cyclone® 10 GX devices support up to 4 streams
- 128B/132B Channel Coding supports up to 4 streams
- 8B/10B Channel Coding supports progressive and interlaced video
- 128B/132B Channel Coding supports progressive video
- Source support for proprietary video image format (optional)
- Support for sink non-GPU mode
- Support for adaptive sync feature
- Support for High Dynamic Range (HDR) metadata transport using secondary stream data packet
- Auxiliary channel for 2-way communication (link and device management)
- Hot plug detect (HPD)
- Sink announces its presence
- Sink requests the source’s attention
- 8B/10B Channel Coding in SST mode supports the High-bandwidth Digital Content Protection (HDCP) feature for Intel® Arria® 10 and Intel® Stratix® 10 devices
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Typical Application |
- Interfaces within a PC or monitor
- External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display
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Device Family Support |
Intel® Agilex™ (F-tile), Intel® Stratix® 10 (H-tile and L-tile), Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V, Cyclone® V, and Stratix® V FPGA devices. |
Design Tools |
- IP Catalog in the Intel® Quartus® Prime software for IP design instantiation and compilation
- Timing Analyzer in the Intel® Quartus® Prime software for timing analysis
- ModelSim* - Intel® FPGA Edition, NCSim, VCS* / VCS* MX, and Xcelium* Parallel software for design simulation
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