Visible to Intel only — GUID: hco1410462529595
Ixiasoft
Visible to Intel only — GUID: hco1410462529595
Ixiasoft
8.1.1. Copy the Simulation Files to Your Working Directory
Copy the simulation example files to your working directory using the command:
cp -r <IP root directory>/altera/altera_dp/sim_example/<device> <working directory>
where <device> is av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices.
Your working directory should contain the files shown below.
File Type |
File |
Description |
---|---|---|
System Verilog HDL design files |
<prefix>_dp_harness.sv |
Top-level test harness. |
Verilog HDL design files |
<prefix>_dp_example.v |
Design under test (DUT). |
dp_mif_mappings.v |
Table translating MIF mappings for transceiver reconfiguration. |
|
dp_analog_mappings.v |
Table translating VOD and pre-emphasis settings. |
|
reconfig_mgmt_hw_ctrl.v |
Reconfiguration manager top-level. |
|
reconfig_mgmt_write.v |
Reconfiguration manager FSM for a single write command. |
|
clk_gen.v |
Clock generation file. |
|
freq_check.sv |
Top-level file for the frequency checker. |
|
rx_freq_check.sv |
RX frequency checker. |
|
tx_freq_check.sv |
TX frequency checker. |
|
vga_driver.v |
VGA driver (generates a test image). |
|
IP Catalog files |
<prefix>_ dp.v |
IP Catalog variant for the DisplayPort Intel® FPGA IP. |
<prefix>_ xcvr_reconfig.v |
IP Catalog variant for the transceiver reconfiguration core. |
|
<prefix>_ native_phy_rx.v |
IP Catalog variant for the RX transceiver. | |
<prefix>_ native_phy_tx.v | IP Catalog variant for the TX transceiver. | |
Scripts |
runall.sh |
This script generates the IP simulation files and scripts, and compiles and simulates them. |
msim_dp.tcl |
Compiles and simulates the design in the ModelSim* software. |
|
Waveform .do files |
all.do |
Waveform that shows a combination of all waveforms. |
reconfig.do |
Waveform that shows the signals involved in reconfiguring the transceiver. |
|
rx_video_out.do |
Waveform that shows the rx_video_out signals from the DisplayPort Intel® FPGA IP mapped to the CVI input. |
|
tx_video_in.do |
Waveform that shows the tx_vid_v_sync, tx_vid_h_sync, de, tx_vid_de, tx_vid_f, and tx_vid_data[23:0] signals at 256 pixels per line and 8 bpp, |
|
Miscellaneous files |
readme.txt |
Documentation for the simulation example. |
edid_memory.hex |
Initial content for the EDID ROM. |