DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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5.9. Source Clock Tree

The source uses the following clocks:

  • Local pixel clock (txN_vid_clk), which clocks video data into the IP.
  • Main link clock (tx_ss_clk), which clocks data out of the IP and into the high-speed serial output (HSSI) components. The main link clock is the output of the PLL clock. You can supply the PLL with the reference clock, 135 MHz for RBR to HBR3, and 100MHz for UHBR10. You can use other frequencies by changing the PLL divider ratios and/or reconfiguring the transceiver. The 20-, 40-, or 32- bit data fed to the HSSI is synchronized to a single HSSI[0] clock. If you select the dual symbol mode, this clock is equal to the link rate divided by 20 (270, 135, or 81 MHz). If you select the quad symbol mode, this clock is equal to the link rate divided by 40 (202.5, 135, 67.5, or 40.5 MHz). If you select DP2.0 UHBR10 data rate, this clock is equal to the link rate divided by 32 (312.5 MHz). The core supports only asynchronous local pixel clock and main link clock.
  • 16 MHz clock (aux_clk), which the IP requires to encode or decode the AUX channel.
  • A separate clock (clk) clocks the Avalon-MM interface.
  • txN_audio_clk for the audio interface.
Figure 27. Source Clock Tree