Visible to Intel only — GUID: rtd1577432074013
Ixiasoft
Visible to Intel only — GUID: rtd1577432074013
Ixiasoft
6.5. HDCP 2.3 RX Architecture
The HDCP 2.3 RX core is fully autonomous. For DisplayPort application, the HDCP transmitter and the HDCP receiver communicates the HDCP register values over the AUX channel. Turn on the Enable GPU control parameter and use a Nios® II processor to drive the HDCP 2.3 RX core through the HDCP Register Port ( Avalon® memory-mapped interface). The HDCP Register Port is not exposed and will be automatically driven when you enable the Support HDCP 2.3 parameter.
The HDCP specifications requires the HDCP 2.3 RX core to be programmed with the DCP-issued production key – Global Constant (lc128), RSA private key (kprivrx) and RSA Public Key Certificate (certrx). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port (rx_hdcp interface). The on-chip memory must store the key data in the arrangement shown in the table below.
Address | Content |
---|---|
8'hE3 | lc128[127:96] |
8'hE2 | lc128[95:64] |
8'hE1 | lc128[63:32] |
8'hE0 | lc128[31:0] |
8'hDF | kprivrx_p[511:480] |
... | ... |
8'hD0 | kprivrx_p[31:0] |
8'hCF | kprivrx_q[511:480] |
... | ... |
8'hC0 | kprivrx_q[31:0] |
8'hBF | kprivrx_dp[511:480] |
... | ... |
8'hB0 | kprivrx_dp[31:0] |
8'hAF | kprivrx_dq[511:480] |
... | ... |
8'hA0 | kprivrx_dq[31:0] |
8'h9F | kprivrx_qinv[511:480] |
... | ... |
8'h90 | kprivrx_qinv[31:0] |
8'h83–8'h8F | Reserved |
8'h82 | {16’d0, certrx[4175:4160]} |
8'h81 | certrx[4159:4128] |
... | ... |
8'h01 | certrx[63:32] |
8'h00 | certrx[31:0] |
The Video Stream and Secondary Data Layer receives audio and video content over its Video and Secondary Data Input Port, and performs the decryption operation. The Video Stream and Secondary Data Layer detects the Encryption Status Signaling (ESS) provided by the DisplayPort IP to determine when to decrypt frames.
To implement the HDCP 2.3 RX core as a repeater upstream interface, the IP must propagate certain information such as ReceiverID List and RxInfo to the upstream transmitter and to be used for HMAC computation. The repeater downstream interface (TX) must provide this information using the Repeater Message Port (rx_rpt_msg interface) using the Avalon® memory-mapped interface. You can use the same clock source to drive the clocking for the HDCP Register Port (or the controller interface of the DisplayPort Intel® FPGA IP) and Repeater Message Port.
The mapping for the RX registers and RX Repeater registers are defined in the following tables.
Address | Register | R/W | Reset | Bit | Bit Name | Description |
---|---|---|---|---|---|---|
0x40 | CTRL | RW | 0x00000000 | 31 | Reserved | Reserved. |
30 | CP_IRQ_DET | Write-only. Set to 1 to reset the CP_IRQ_STATUS flag in the RXSTATUS register. | ||||
29 | STOP_DET | Write-only. Set to 1 to indicate the end of HDCP messages. | ||||
28:1 | Reserved | Reserved. | ||||
0 | TYPE | 0: Type 0 content stream. 1: Type 1 content stream. |
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0x41 | RXSTATUS | RO | 0x00000000 | 31:19 | Reserved | Reserved. |
18 | CP_IRQ_STATUS | 0: No HDCP 2.3 event. 1: An HDCP 2.3 event occurred and HPD interrupts were generated. |
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17:5 | Reserved | Reserved. | ||||
4 | LINK_INTEGRITY_FAILURE | RxStatus[4:0]. Refer to the HDCP on DisplayPort Specification version 2.3 for more information. |
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3 | REAUTH_IRQ | |||||
2 | PAIRING_AVAILABLE | |||||
1 | HPRIME_AVAILABLE | |||||
0 | READY | |||||
0x42 | MESSAGES | RW | 0x00000000 | 31:8 | Reserved | Reserved. |
7:0 | MESSAGES | Write or read messages (in bytes) to or from the IP in burst mode. | ||||
0x43 | RXCAPS | RO | 0x00020002 | 31:24 | Reserved | Reserved. |
23:16 | VERSION | Default value is 0x02. | ||||
15:2 | RECEIVER_CAPABILITY_MASK | Reserved. Read as 0. | ||||
1 | HDCP_CAPABLE | Default value is 0x01. Indicates that the RX is HDCP 2.3 capable. | ||||
0 | REPEATER | 0: Indicates that the RX is an endpoint receiver. 1: Indicates that the RX is a repeater that supports downstream connections. |
Address | Register | R/W | Reset | Bit | Bit Name | Description |
---|---|---|---|---|---|---|
0x00 | RPT_RCVDID_LIST | WO | 0x00000000 | 31:8 | Reserved | Reserved |
7:0 | RCVDID_LIST | Byte write ReceiverID_List in big endian order. | ||||
0x01 | RPT_RXINFO | RW | 0x00000000 | 31:19 | Reserved | Reserved |
18 | REQUEST | Read-only. Asserted by the core to request for RCVDID_LIST and RXINFO. This usually happens when re-authentication is triggered by the connected upstream. Note that when REQUEST is asserted, the READY should also be asserted. | ||||
17 | READY | Read-only. Asserted by the core to indicate RCVDID_LIST and RXINFO are processed. Write RCVDID_LIST and RXINFO after this bit is asserted. | ||||
16 | VALID | Set to 1 after RCVDID_LIST and RXINFO are written. Self-cleared by the core after RCVDID_LIST and RXINFO are read. | ||||
15:0 | RXINFO | [15:12]: Reserved. [11:9]: DEPTH [8:4]: DEVICE_COUNT [3]: MAX_DEVS_EXCEEDED [2]: MAX_CASCADE_EXCEEDED [1]: HDCP2_REPEATER_DOWNSTREAM [0]: HDCP1_DEVICE_DOWNSTREAM |
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0x02 | RPT_TYPE | RO | 0x00000000 | 31:9 | Reserved | Reserved |
8 | VALID | Asserted by the core to indicate content stream TYPE is valid. Self-cleared by the core after TYPE is read. | ||||
7:0 | TYPE | 0x00: Type 0 Content Stream 0x01: Type 1 Content Stream 0x02-0xFF: Reserved. Treated as Type 1 Content Stream. |
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0x03 | RPT_MISC | RW | 0x00000000 | 31:1 | Reserved | Reserved. |
0 | REPEATER | Set to 0 if no downstream is connected or if the connected downstream is not HDCP 2.3-capable. This means the receiver IP is an end-point receiver rather than a repeater. Set to 1 if the connected downstream is HDCP- capable. |