Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683267
Date 3/28/2022
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1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Developing Your Intel® Arria® 10 Custom Platform 3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform x
1.2.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Board Variants
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases x
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0 1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1 1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0 1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1 1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1
2. Developing Your Intel® Arria® 10 Custom Platform x
2.1. Initializing Your Intel® Arria® 10 Custom Platform 2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment 2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication 2.6. Branding Your Intel® Arria® 10 Custom Platform 2.7. Changing the Device Part Number 2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform 2.9. Modifying the Kernel PLL Reference Clock 2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform 2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform 2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform x
2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture x
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® 3.2. DDR4 as Global Memory for OpenCL Applications 3.3. Host Connection to OpenCL Kernels 3.4. Intel® Arria® 10 FPGA System Design 3.5. Dynamic PLL Reconfiguration 3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 3.7. Intel® Quartus® Prime Compilation Flow and Scripts 3.8. Addition of Timing Constraints 3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.10. Intel® Arria® 10 FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts 3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® x
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access 3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP 3.1.3. Instantiation of the version_id Component 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files 3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 3.1.6. Direct Memory Access 3.1.7. Message Signaled Interrupt 3.1.8. Partial Reconfiguration 3.1.9. Cable Autodetect 3.1.10. Host Channel
3.1.6. Direct Memory Access x
3.1.6.1. Implementing a DMA Transfer
3.1.10. Host Channel x
3.1.10.1. Host Channel IP Instantiation 3.1.10.2. Host Channel Top Connection to PCIe* DMA 3.1.10.3. Host Channel Top Connection to OpenCL Kernel
3.2. DDR4 as Global Memory for OpenCL Applications x
3.2.1. DDR4 IP Instantiation 3.2.2. DDR4 Connection to PCIe Host 3.2.3. DDR4 Connection to the OpenCL Kernel
3.4. Intel® Arria® 10 FPGA System Design x
3.4.1. Clocks 3.4.2. Resets 3.4.3. Floorplan 3.4.4. Global Routing 3.4.5. Pipelining 3.4.6. DDR4 Calibration 3.4.7. Kernel Reprogramming via Partial Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design x
3.6.1. Supply the Kernel Clock 3.6.2. Guarantee Kernel Clock Timing 3.6.3. Provide a Timing-Closed Post-Fit Netlist
3.7. Intel® Quartus® Prime Compilation Flow and Scripts x
3.7.1. Enabling the Intel® Quartus® Prime Forward-Compatibility Flow 3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers 3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users 3.7.4. Platform Designer System Generation 3.7.5. QDB File Generation 3.7.6. Hash Checking
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow x
3.10.1. Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
3.12.5. aocl diagnose x
3.12.5.1. Possible Errors After Running the diagnose Utility
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform

Familiarize yourself with directories and files within the Intel® Arria® 10 GX FPGA Development Kit Reference Platform ( INTELFPGAOCLSDKROOT/board/s10_ref because they are referenced throughout this document.
Table 1.  Highlights of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Directory
Windows File or Folder Linux File or Directory Description
board_env.xml board_env.xml eXtensible Markup Language (XML) file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ .
hardware hardware Contains the Intel® Quartus® Prime project templates for the a10gx board variant.

See Contents of the a10gx Directory for a list of files in this directory.

windows64 linux64 Contains the MMD library, kernel mode driver, and executable files of the SDK utilities (that is, install, uninstall, flash, program, diagnose) for your 64-bit operating system.
source source

For Windows, the source folder contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the windows64 folder.

For Linux, the source directory contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the linux64 directory.

Table 2.  Contents of the a10gx DirectoryThe following table lists the files in the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx directory, where INTELFPGAOCLSDKROOT points to the location of the SDK installation.
File Description
mem.qsys Platform Designer system that, together with the .ip files in the ip/mem subdirectory, implements the mem component.
ddr4.qsys Platform Designer system that, together with the .ip files in the ip/ddr4 subdirectory, implements the ddr4 component.
base.qsf Intel® Quartus® Prime Settings File for the base project revision. This file includes, by reference, all the settings in the flat.qsf file.

Use this revision when porting the a10_ref Reference Platform to your own Custom Platform. The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code.

base.qar Intel® Quartus® Prime Archive File that contains base.qdb, pr_base.id, and base.sdc. This file is generated by the scripts/post_flow_pr.tcl file during base revision compile, and is used during import revision compilation.
base.qdb
Intel® Quartus® Prime Database Export File that contains the precompiled netlist of the static regions of the design.
pr_base.id
Text file containing a unique number for a given base compilation that the runtime uses to determine whether it is safe to use PR programming.
base.sdc
Synopsys Design Constraints File that the Intel® Quartus® Prime software autogenerates during a base compilation. The base.sdc file is used in the top revision compilation to import all the timing constraints from the static region.
board.qsys Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system.
board_spec.xml XML file that provides the definition of the board hardware interfaces to the SDK.
device.tcl Tcl file that is included in all revisions and contains all device-specific information (for example, device family, ordering part number (OPN), and voltage settings).
flat.qsf Intel® Quartus® Prime Settings File for the flat project revision. This file includes all the common settings, such as pin location assignments, that are used in the other revisions of the project (that is, base, top, and top_synth). The base.qsf, top.qsf, and top_synth.qsf files include, by reference, all the settings in the flat.qsf file.

The Intel® Quartus® Prime software compiles the flat revision with minimal location constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow.

import_compile.tcl Tcl script for the SDK-user compilation flow (that is, import revision compilation).
max5_150.pof Programming file for the MAX® V device on the Intel® Arria® 10 GX FPGA Development Kit that sets the memory reference clock to 150 MHz by default at power-up.

You must program the max5_150.pof file onto your a10gx board.

opencl_bsp_ip.qsf Intel® Quartus® Prime Settings File that collects all the required .ip files in a unique location.

During flat and base revision compilations, the board.qsys, mem.qsys and ddr4.qsys Platform Designer files are added to the opencl_bsp_ip.qsf file.

reset_2x.sdc Synopsys Design Constraints file with timing constraints for reset synchronizers on the 2x kernel clock.
quartus.ini Contains any special Intel® Quartus® Prime software options that you need to compile OpenCL kernels for the a10_ref Reference Platform.
top.qpf Intel® Quartus® Prime Project File for the OpenCL hardware system.
top.qsf Intel® Quartus® Prime Settings File for the SDK-user compilation flow.
top.sdc Synopsys Design Constraints file that contains board-specific timing constraints.
top.v Top-level Verilog Design file for the OpenCL hardware system.
top_post.sdc Platform Designer and Intel® FPGA SDK for OpenCL™ IP-specific timing constraints.
top_synth.qsf Intel® Quartus® Prime Settings File for the Intel® Quartus® Prime revision in which the OpenCL kernel system is synthesized.
ip/mem/<file_name> Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the mem component.

You must provide both the mem.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.

ip/ddr4/<file_name> Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the ddr4 component.

You must provide both the ddr4.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.

ip/board/<file_name> Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the board instance.

You must provide both the board.qsys file and the corresponding .ip files in this directory to the Intel® Quartus® Prime Pro Edition software.

ip/freeze_wrapper.v Verilog Design File that implements the freeze logic placed at outputs of the Partial Reconfiguration region.
ip/irq_controller/<file_name> IP that receives interrupts from the OpenCL kernel system and sends message signaled interrupts (MSI) to the host.

Refer to the Message Signaled Interrupts section for more information.

ip/host_channel IP that implements the DMA descriptor controller as well as AVMM-to-AVST and AVST-to-AVMM between DMA and kernel.
Attention: This IP is available only in the a10gx_hostch board variant.
scripts/base_write_sdc.tcl Tcl script that the base revision compilation uses to generate the base.sdc file containing all the constraints collected in the base revision compilation. The Intel® Quartus® Prime Pro Edition software uses the base.sdc file when compiling the import (top) revision.
scripts/create_fpga_bin_pr.tcl Tcl script that generates the fpga.bin file. The fpga.bin file contains all the necessary files for configuring the FPGA.

For more information on the fpga.bin file, refer to the Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform section.

scripts/post_flow_pr.tcl Tcl script that implements the guaranteed timing closure flow, as described in the Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design section.
scripts/pre_flow_pr.tcl Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys and kernel_system.qsys. It also creates a unique ID for the PR base revision (that is, static region). This unique ID is stored in the pr_base.id file.
scripts/regenerate_cache.tcl Tcl script that regenerates the BAK cache file in your temporary directory.
scripts/qar_ip_files.tcl Tcl script that packages up base.qdb, pr_base.id and base.sdc during base revision compile.
scripts/create_acds_ver_hex.tcl Tcl script called by the pre_flow_pr.tcl script to create contents of the ACDS version ROM.
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