Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683267
Date 3/28/2022
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1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Developing Your Intel® Arria® 10 Custom Platform 3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform x
1.2.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Board Variants
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases x
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0 1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1 1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0 1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1 1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1 Removing the Multicycle Reset Constraint Creating Copies of the Kernel Clock Instantiating the Reset Synchronizer Modifying the Floorplan Completing the Changes
2. Developing Your Intel® Arria® 10 Custom Platform x
2.1. Initializing Your Intel® Arria® 10 Custom Platform 2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment 2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication 2.6. Branding Your Intel® Arria® 10 Custom Platform 2.7. Changing the Device Part Number 2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform 2.9. Modifying the Kernel PLL Reference Clock 2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform 2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform 2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform x
2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture x
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® 3.2. DDR4 as Global Memory for OpenCL Applications 3.3. Host Connection to OpenCL Kernels 3.4. Intel® Arria® 10 FPGA System Design 3.5. Dynamic PLL Reconfiguration 3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 3.7. Intel® Quartus® Prime Compilation Flow and Scripts 3.8. Addition of Timing Constraints 3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.10. Intel® Arria® 10 FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts 3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® x
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access 3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP 3.1.3. Instantiation of the version_id Component 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files 3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 3.1.6. Direct Memory Access 3.1.7. Message Signaled Interrupt 3.1.8. Partial Reconfiguration 3.1.9. Cable Autodetect 3.1.10. Host Channel
3.1.6. Direct Memory Access x
3.1.6.1. Implementing a DMA Transfer
3.1.10. Host Channel x
3.1.10.1. Host Channel IP Instantiation 3.1.10.2. Host Channel Top Connection to PCIe* DMA 3.1.10.3. Host Channel Top Connection to OpenCL Kernel
3.2. DDR4 as Global Memory for OpenCL Applications x
3.2.1. DDR4 IP Instantiation 3.2.2. DDR4 Connection to PCIe Host 3.2.3. DDR4 Connection to the OpenCL Kernel
3.4. Intel® Arria® 10 FPGA System Design x
3.4.1. Clocks 3.4.2. Resets 3.4.3. Floorplan 3.4.4. Global Routing 3.4.5. Pipelining 3.4.6. DDR4 Calibration 3.4.7. Kernel Reprogramming via Partial Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design x
3.6.1. Supply the Kernel Clock 3.6.2. Guarantee Kernel Clock Timing 3.6.3. Provide a Timing-Closed Post-Fit Netlist
3.7. Intel® Quartus® Prime Compilation Flow and Scripts x
3.7.1. Enabling the Intel® Quartus® Prime Forward-Compatibility Flow 3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers 3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users 3.7.4. Platform Designer System Generation 3.7.5. QDB File Generation 3.7.6. Hash Checking
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow x
3.10.1. Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
3.12.5. aocl diagnose x
3.12.5.1. Possible Errors After Running the diagnose Utility
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1

If you use or have modified an Intel® Arria® 10 GX FPGA Development Kit Reference Platform BSP provided for Intel® Quartus® Prime Design Suite Version 18.1, review the following information to learn about changes implemented in the BSP for Version 19.1.

In Intel® Quartus® Prime Design Suite Version 19.1, the multicycle constraint on kernel reset was removed. This change prevents IPs from coming out of reset on different cycles. Though generated OpenCL kernels should not have state transitions when coming out of reset, this change guarantees functionality for any IP on the kernel clock domain.

Files located in the INTELFPGAOCLSDKROOT/board/a10_ref/ directory in the BSP have the following changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1:

Table 7.  Changes in a10_ref Reference Platform from 18.1 to 19.1
File Change
hardware/a10gx_hostch/* Directory renamed as a10gx_hostpipe.
hardware/a10gx_hostpipe/board_spec.xml Changed the board name to a10gx_hostpipe.
hardware/a10gx_hostpipe/base.qsf Cleaned up the floorplan to be similar to a10gx board variant.
hardware/a10gx_hostpipe/ip/host_channel/acl_hostchannel_top_hw.tcl Changed the readyLatency value from 2 to 3.
  • base.qar
  • base.qsf
  • flat.qsf
  • board.qsys
  • ip/freeze_wrapper.v
  • top.v
  • top_post.sdc
  • reset_2x.sdc
  • scripts/post_flow_pr.tcl
  • hw_iface.iipx
  • sw_iface.iipx
Removed multicycle reset constraint. For more information, refer to Removing the Multicycle Reset Constraint.
reset_2x.sdc Added this file to both board variants in a10_ref BSP.
If you are using a BSP from an earlier version, refer to the following sections to modify files in your BSP to change the reset behavior:
Tip: If you have not modified files listed in the Changes in a10_ref Reference Platform from 18.1 to 19.1 table in your BSP, you can replace the respective files with the corresponding files from the 19.1 BSP instead of modifying them.

Removing the Multicycle Reset Constraint

Follow these steps to modify the timing constraint file top_post.sdc (located in the hardware directory of your BSP) to remove the multicycle reset constraint:

  1. Remove four lines after the comment # Make the kernel reset multicycle (originally at line 91 in the top_post.sdc file).
  2. Add the lines following the comment # cut path from reset to synchronizer (now at line 90) and # over-constrain the delay from the synchronizer (at line 108) of the a10_ref/hardware/a10gx/top_post.sdc file in the 19.1 a10_ref BSP to the top_post.sdc file of your BSP. 
# cut path from reset to synchronizer  
set_false_path -from {freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n} \
-to  {freeze_wrapper_inst|acl_reset_handler_inst|*} 

# overconstrain the delay from the synchronizer to the global buffer to 
# help recovery timing 
set_max_delay 1 -from  \
freeze_wrapper_inst|acl_reset_handler_inst|GEN_SYNCHRONIZER.synchronizer_body[1] \
-to freeze_wrapper_inst|acl_reset_handler_inst|GEN_SYNCHRONIZER.synchronizer_body[1] \
~CLKENA0|outclk

Creating Copies of the Kernel Clock

To improve kernel performance without the multicycle reset constraint, synchronize the reset going into the kernel by using a copy of the kernel clock distributed on a periphery clock network, which has a lower delay. Follow these steps to modify the board.qsys file located in the hardware directory of your BSP to create copies of the kernel clock on separate global and periphery networks:

  1. Replace hw_iface.iipx and sw_iface.iipx files with the ones from the 19.1 BSP folder.
  2. Open the board.qsys file in Platform Designer.
  3. For the acl_kernel_interface IP, change the Make kernel reset a global signal parameter value from 1 to 0.
  4. Instantiate an A10 Global Clock Enable component and an A10 Periph Clock Enable component (both components are in the ACL Internal Components category).
  5. Connect the 1x clock of the kernel clock generator to the input of both components.
  6. Export the output of the A10 Periph Clock Enable as reset_sync_clk.
  7. Connect all components in the board.qsys file (which are connected directly to the 1x clock of the kernel clock generator) to the clock from the output of the A10 Global Clock Enable.
  8. Regenerate the system, which updates .ip files in the ip/board/ directory.

Instantiating the Reset Synchronizer

Follow these steps to instantiate the reset synchronizer in the ip/freeze_wrapper.v file located in the hardware directory of your BSP:

  1. Add a new wire to the top.v file to connect the new output of board_inst to the new input port board_reset_sync_clk of the freeze_wrapper.v file.
  2. Add the new input port to the ip/freeze_wrapper.v file.
  3. Add a new signal for the synchronized reset.
  4. Instantiate the acl_reset_handler as indicated between lines 117 and 130 in the a10_ref/hardware/a10gx/ip/freeze_wrapper.v file in the 19.1 a10_ref BSP.
  5. Connect the new synchronized reset to the port clock_reset_reset_reset_n of pr_region_inst.

Modifying the Floorplan

You must update the floorplan in the base revision to allow the reset synchronizer to be placed as close as possible to the PLL. If the reference clock input pin is the same as in the 19.1 a10_ref BSP, the same regions and constraints can be used.

Follow these steps to modify the floorplan:

  1. Create a 1x1 region adjacent to the PLL that can be added to the static region. This can be performed by first creating a 1x1 floorplan region, and then subtracting it from the Partial Reconfiguration (PR) region.
  2. To improve timing closure of the base compile, provide a location constraint to global clock buffer, periphery clock buffer, and reset synchronizer as close as possible to the PLL, as indicated between lines 54 to 56 of the a10_ref/hardware/a10gx/ip/base.qsf file in the 19.1 a10_ref BSP: 
# location constraint these global buffers and synchronization register to 
# help recovery timing. 
set_location_assignment CLKCTRL_3A_G_I21 \
-to freeze_wrapper_inst|acl_reset_handler_inst|GEN_SYNCHRONIZER.synchronizer_body[1]~CLKENA0 
set_location_assignment FF_X143_Y17_N26 \
-to freeze_wrapper_inst|acl_reset_handler_inst|GEN_SYNCHRONIZER.synchronizer_body[1] 
set_location_assignment CLKCTRL_3A_P15_I6 \
-to board_inst|kclk_periph|periph_clkena_0|clkena

Completing the Changes

To complete the changes, perform the following steps in the hardware directory of your BSP:

  1. In the scripts/post_flow_pr.tcl file, add the following line before the line source "$sdk_root/ip/board/bsp/adjust_plls.tcl” (as in line 64 of the 19.1 a10_ref BSP):
    set recovery_multicycle 1.0
  2. In the flat.qsf file, perform the following changes:
    1. Remove the following line that was originally at line 61:
      set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK \
-to board_inst|kernel_clk_gen|kernel_clk_gen|kernel_pll|altera_pll_i \
|twentynm_pll|outclk[0]
    2. Replace two references to freeze_wrapper_inst|kernel_system_clock_reset_reset_reset_n with freeze_wrapper_inst|acl_reset_handler_inst|GEN_SYNCHRONIZER.synchronizer_body[1].
  3. Copy the reset_2x.sdc file from 19.1 a10_ref BSP to the hardware directory of your BSP and add the following assignment after the assignment that adds top_post.sdc to your project in flat.qsf. 
    # SDC file needed for 2x clock reset synchronizaion 
set_global_assignment -name SDC_FILE reset_2x.sdc

Now, you can perform the base compile to generate a new base.qar.

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