Visible to Intel only — GUID: ewa1437421928900
Ixiasoft
Visible to Intel only — GUID: ewa1437421928900
Ixiasoft
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
The Intel® Arria® 10 GX FPGA Development Kit Reference Platform targets a subset of the hardware features available in the Intel® Arria® 10 GX FPGA Development Kit.
Features of the a10_ref Reference Platform:
- OpenCL Host
The a10_ref Reference Platform uses a PCIe-based host that connects to the Intel® Arria® 10 PCIe Gen3x8 hard IP core.
- OpenCL Global Memory
The hardware provides one 2-gigabyte (GB) DDR4 SDRAM daughtercard that is mounted on the HiLo connector (J14 in Hardware Features of the Intel® Arria® 10 GX FPGA Development Kit).
- FPGA Programming via one of the following methods:
- Partial Reconfiguration (PR) over PCIe* .
- External cable and the Intel® Arria® 10 GX FPGA Development Kit's on-board Intel® FPGA Download Cable II interface.
- External Intel FPGA Download Cable II interface connected to a 10-pin JTAG header.
- Guaranteed Timing
The a10_ref Reference Platform relies on the Intel® Quartus® Prime Pro Edition compilation flow to provide guaranteed timing closure. The timing-clean a10_ref Reference Platform is preserved in the form of a precompiled post-fit netlist (that is, the base.qdb Intel® Quartus® Prime Database Export File). The Intel® FPGA SDK for OpenCL™ Offline Compiler imports this preserved post-fit netlist into each OpenCL kernel compilation.
- OpenCL Host Pipe
Using direct memory access (DMA) in Intel® Arria® 10 PCIe* Gen3 x8 hard IP core a10gx_hostch board variant has a direct host to kernel and kernel to host pipe.