Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Public
Document Table of Contents

1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1

If you use or have modified an Intel® Arria® 10 GX FPGA Development Kit Reference Platform BSP provided for Intel® Quartus® Prime Design Suite Version 18.0, review the following information to learn about changes implemented in the BSP for Version 18.1.

The files in the BSP have the following changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1:

Table 6.  Changes in a10_ref Reference Platform from 18.0 to 18.1
File Change
base.qsf Removed the Logic Lock region assignments.
board_spec.xml Changed OPN to production silicon.
device.tcl Decreased the core voltage from 950mV to 900mV.
top_post.sdc Added a clock uncertainty between 1x and 2x clocks to avoid hold time violations.
scripts/helpers.tcl Added a new script.
scripts/pre_flow_pr.tcl Added the incremental compile support.