Visible to Intel only — GUID: ewa1437424385531
Ixiasoft
Visible to Intel only — GUID: ewa1437424385531
Ixiasoft
3.10. Intel® Arria® 10 FPGA Programming Flow
In the order from the longest to the shortest configuration time, the three FPGA programming methods are as follows:
- To replace both the FPGA periphery and the core while maintaining the programmed state after power cycling, use Flash programming.
- To replace both the FPGA periphery and the core, use the Intel® Quartus® Prime Programmer command-line executable (quartus_pgm) to program the device via cables such as the Intel® FPGA Download Cable (formerly USB-Blaster).
- To replace only the kernel portion of the device, use PR.
The default FPGA programming flow is to use PR over PCIe* . The Partial Reconfiguration Controller IP instantiates PR over PCIe* using the following IP parameter settings:
Parameter | Setting |
---|---|
Settings | |
Use as PR Internal Host | Enabled |
Enable Avalon-MM agent interface | Enabled |
Input data width | 32 bits |
Clock-to-Data ratio | 1 |
Divide error detection frequency by | 1 |
Advanced Settings | |
Auto-instantiate PR block | Enabled |
Auto-instantiate CRC block | Enabled |
The 50 MHz config_clk clocks the Partial Reconfiguration Controller IP. The Avalon® -MM interface connects to the host control bus on PCIe* BAR4. Using PCIe* Gen3x8 under these configuration settings, the duration of partial reconfiguration of the PR region is about 1.6 seconds.
You cannot use PR if there is a mismatch between the hash within the .aocx file and the hash in the static region of the current image on the FPGA. In this case, program the FPGA via Intel® FPGA Download Cable by invoking quartus_pgm instead. If the .aocx file is not PR compatible with the current image on the FPGA, the Intel® Quartus® Prime Programmer displays the following message:
aocl program acl0 boardtest.aocx aocl program: Running program from <path_to_a10_ref>/linux64/libexec Reprogramming device with handle 1 MMD INFO : [acla10_ref0] PR base and import compile IDs do not match MMD INFO : [acla10_ref0] PR base ID currently configured is 0x7d056bf2 MMD INFO : [acla10_ref0] PR import compile expects ID to be 0x30242eb9 mmd program_device: Board reprogram failed
Only use quartus_pgm via Intel® FPGA Download Cable if you use a cable to connect the board and the host computer. Cabling is a point of potential failure, and it does not scale well to large deployments. If possible, reserve the quartus_pgm programming approach for development and testing purposes only.
If PR fails, an attempt is automatically made to detect the Intel® FPGA Download Cable and do a full JTAG programming.