Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683267
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Developing Your Intel® Arria® 10 Custom Platform 3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture 4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives 5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform x
1.2.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Board Variants
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases x
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0 1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1 1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0 1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1 1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1
2. Developing Your Intel® Arria® 10 Custom Platform x
2.1. Initializing Your Intel® Arria® 10 Custom Platform 2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment 2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication 2.6. Branding Your Intel® Arria® 10 Custom Platform 2.7. Changing the Device Part Number 2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform 2.9. Modifying the Kernel PLL Reference Clock 2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform 2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform 2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform x
2.11.1. Generating the base.qar Post-Fit Netlist for Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture x
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® 3.2. DDR4 as Global Memory for OpenCL Applications 3.3. Host Connection to OpenCL Kernels 3.4. Intel® Arria® 10 FPGA System Design 3.5. Dynamic PLL Reconfiguration 3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design 3.7. Intel® Quartus® Prime Compilation Flow and Scripts 3.8. Addition of Timing Constraints 3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.10. Intel® Arria® 10 FPGA Programming Flow 3.11. Host-to-Device MMD Software Implementation 3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts 3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe® x
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access 3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP 3.1.3. Instantiation of the version_id Component 3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files 3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform 3.1.6. Direct Memory Access 3.1.7. Message Signaled Interrupt 3.1.8. Partial Reconfiguration 3.1.9. Cable Autodetect 3.1.10. Host Channel
3.1.6. Direct Memory Access x
3.1.6.1. Implementing a DMA Transfer
3.1.10. Host Channel x
3.1.10.1. Host Channel IP Instantiation 3.1.10.2. Host Channel Top Connection to PCIe* DMA 3.1.10.3. Host Channel Top Connection to OpenCL Kernel
3.2. DDR4 as Global Memory for OpenCL Applications x
3.2.1. DDR4 IP Instantiation 3.2.2. DDR4 Connection to PCIe Host 3.2.3. DDR4 Connection to the OpenCL Kernel
3.4. Intel® Arria® 10 FPGA System Design x
3.4.1. Clocks 3.4.2. Resets 3.4.3. Floorplan 3.4.4. Global Routing 3.4.5. Pipelining 3.4.6. DDR4 Calibration 3.4.7. Kernel Reprogramming via Partial Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design x
3.6.1. Supply the Kernel Clock 3.6.2. Guarantee Kernel Clock Timing 3.6.3. Provide a Timing-Closed Post-Fit Netlist
3.7. Intel® Quartus® Prime Compilation Flow and Scripts x
3.7.1. Enabling the Intel® Quartus® Prime Forward-Compatibility Flow 3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers 3.7.3. Intel® Quartus® Prime Compilation Flow for Custom Platform Users 3.7.4. Platform Designer System Generation 3.7.5. QDB File Generation 3.7.6. Hash Checking
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ x
3.9.1. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 3.9.2. Describe the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow x
3.10.1. Define the Contents of the fpga.bin File for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
3.12.1. aocl install 3.12.2. aocl uninstall 3.12.3. aocl program 3.12.4. aocl flash 3.12.5. aocl diagnose 3.12.6. aocl list-devices
3.12.5. aocl diagnose x
3.12.5.1. Possible Errors After Running the diagnose Utility
1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites

The Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide assumes that you are an experienced FPGA designer familiar with Intel® 's FPGA design tools and concepts.

Prerequisites for the altera_a10pciedk Reference Platform:

  • An Intel® Arria® 10-based accelerator card with working PCI Express* ( PCIe* ) and memory interfaces

    Test these interfaces together in the same design using the same version of the Intel® Quartus® Prime Pro Edition software that you will use to develop your Custom Platform.

    Attention:

    The native Arria 10 GX FPGA Development Kit does not automatically work with the SDK. Before using the Arria 10 GX FPGA Development Kit with the SDK, you must first contact your field applications engineer or regional support center representative to configure the development kit for you.

  • Intel® Quartus® Prime Pro Edition software
  • Designing with Logic Lock regions

General prerequisites:

  • FPGA architecture, including clocking, global routing, and I/Os
  • High-speed design
  • Timing analysis
  • Platform Designer design and Avalon® interfaces
  • Tcl scripting
  • PCIe
  • DDR4 external memory

This document also assumes that you are familiar with the following Intel® FPGA SDK for OpenCL™ -specific tools and documentation:

  • Custom Platform Toolkit and the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide
  • Stratix® V Network Reference Platform (s5_net) and the Stratix V Network Reference Platform Porting Guide

    The memory-mapped device (MMD) and driver software stack in the a10_ref Reference Platform is derived from the s5_net Reference Platform design.

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