Visible to Intel only — GUID: ewa1437423538486
Ixiasoft
Visible to Intel only — GUID: ewa1437423538486
Ixiasoft
3.2. DDR4 as Global Memory for OpenCL Applications
In the current version of the a10_ref Reference Platform, all Platform Designer components related to the DDR4 global memory are now part of the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/acl_ddr4_a10.qsys Platform Designer subsystem within board.qsys. In addition, the location of the clock domain crossings has changed to increase the number of blocks operating in the slower PCIe* domain. With this modified structure, you can add multiple memories with different clock domains to the system.
If you have a Custom Platform that is ported from a previous version of the a10_ref Reference Platform, you have the option to modify your Custom Platform as described above. This modification is not mandatory.
Dependencies
DDR4 external memory interfaces
For more information about the DDR4 external memory interface IP, refer to the DDR2, DDR3, and DDR4 SDRAM Board Design Guidelines section in External Memory Interface Handbook Volume 2: Design Guidelines.
Section Content
DDR4 IP Instantiation
DDR4 Connection to PCIe Host
DDR4 Connection to the OpenCL Kernel