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1. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Developing Your Intel® Arria® 10 Custom Platform
3. Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design Architecture
4. Intel® FPGA SDK for OpenCL™ Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide Archives
5. Document Revision History for the Intel Arria 10 GX FPGA Development Kit Reference Platform Porting Guide
1.1. Intel® Arria® 10 GX FPGA Development Kit Reference Platform: Prerequisites
1.2. Features of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
1.3. Contents of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
1.4. Intel Arria 10 GX FPGA Development Kit Reference Platform BSP Changes Between Intel® Quartus® Prime Design Suite Releases
1.4.1. BSP Changes from Intel® Quartus® Prime Design Suite Version 16.1 to Version 17.0
1.4.2. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.0 to Version 17.1
1.4.3. BSP Changes from Intel® Quartus® Prime Design Suite Version 17.1 to Version 18.0
1.4.4. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.0 to Version 18.1
1.4.5. BSP Changes from Intel® Quartus® Prime Design Suite Version 18.1 to Version 19.1
2.1. Initializing Your Intel® Arria® 10 Custom Platform
2.2. Modifying the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design
2.3. Integrating Your Intel® Arria® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™
2.4. Setting up the Intel® Arria® 10 Custom Platform Software Development Environment
2.5. Establishing Intel® Arria® 10 Custom Platform Host Communication
2.6. Branding Your Intel® Arria® 10 Custom Platform
2.7. Changing the Device Part Number
2.8. Connecting the Memory in the Intel® Arria® 10 Custom Platform
2.9. Modifying the Kernel PLL Reference Clock
2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform
2.11. Guaranteeing Timing Closure in the Intel® Arria® 10 Custom Platform
2.12. Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues
3.1. Host-to- Intel® Arria® 10 FPGA Communication over PCIe®
3.2. DDR4 as Global Memory for OpenCL Applications
3.3. Host Connection to OpenCL Kernels
3.4. Intel® Arria® 10 FPGA System Design
3.5. Dynamic PLL Reconfiguration
3.6. Guaranteed Timing Closure of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform Design
3.7. Intel® Quartus® Prime Compilation Flow and Scripts
3.8. Addition of Timing Constraints
3.9. Connection of the Intel® Arria® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™
3.10. Intel® Arria® 10 FPGA Programming Flow
3.11. Host-to-Device MMD Software Implementation
3.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities
3.13. Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts
3.14. Considerations in Intel® Arria® 10 GX FPGA Development Kit Reference Platform Implementation
3.1.1. Instantiation of Intel® Arria® 10 PCIe* Hard IP with Direct Memory Access
3.1.2. Device Identification Registers for Intel® Arria® 10 PCIe Hard IP
3.1.3. Instantiation of the version_id Component
3.1.4. Definitions of Intel® Arria® 10 FPGA Development Kit Reference Platform Hardware Constraints in Software Headers Files
3.1.5. PCIe Kernel Driver for the Intel® Arria® 10 GX FPGA Development Kit Reference Platform
3.1.6. Direct Memory Access
3.1.7. Message Signaled Interrupt
3.1.8. Partial Reconfiguration
3.1.9. Cable Autodetect
3.1.10. Host Channel
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2.10. Integrating an OpenCL Kernel in Your Intel® Arria® 10 Custom Platform
After you establish host communication and connect the external memory, test the FPGA programming process from kernel creation to program execution.
- Perform the steps outlined in INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt file to build the hardware configuration file from the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl kernel source file.
The environment variable INTELFPGAOCLSDKROOT points to the location of the Intel® FPGA SDK for OpenCL™ installation.
- Program your FPGA device with the hardware configuration file you created in step 1 and then restart your system.
- Remove the early-exit modification in the version_id_test function in the acl_pcie_device.cpp file that you implemented when you established communication between the board and the host interface.
For Windows/Linux, the acl_pcie_device.cpp file is in the <your_custom_platform>\source\host\mmd folder.
- Invoke the aocl diagnose <device_name> command, where <device_name> is the string you define in your Custom Platform to identify each board.
By default, <device_name> is the acl number (for example, acl0 to acl31) that corresponds to your FPGA device. In this case, invoke the aocl diagnose acl0 command.
- Build the boardtest host application using the .sln file (Windows) or Makefile (Linux) in the SDK's Custom Platform Toolkit.
For Windows, the .sln file for Windows is in the INTELFPGAOCLSDKROOT\board\custom_platform_toolkit\tests\boardtest\host folder. For Linux, the Makefile is in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest directory.
- Set the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA to a value of 3 and run the boardtest host application.
For more information about CL_CONTEXT_COMPILER_MODE_INTELFPGA, refer to Troubleshooting Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Issues.