Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Public
Document Table of Contents

3.1.8. Partial Reconfiguration

The Intel® Arria® 10 GX FPGA Development Kit Reference Platform uses partial reconfiguration (PR) as a default mechanism to reconfigure the OpenCL kernel-related partition of the design without altering the static board interface that is in a running state.

You can only use PR when the static board interface, generated during base compilations, matches the static region of the design that is used to compile the OpenCL kernel's PR region.

For Windows MMD implementation, the INTELFPGAOCLSDKROOT\board\a10_ref\source\host\mmd\acl_pcie_config.cpp file contains the MMD code that communicates with the PR configuration controller within the static region of the design. The program_core_with_PR_file function within the acl_pcie_config.cpp file requires a handle to the PR bitstream and the length of the PR bitstream in order to perform the PR operation.

For Linux driver implementation, the INTELFPGAOCLSDKROOT/board/a10_ref/linux64/driver/aclpci_pr.c file includes the main host driver routine that communicates with the PR configuration controller within the static region of the design. The aclpci_pr function within the acl_pci_pr.c file requires the following information in order to perform the PR operation:

  • A handle to the board
  • A handle to the PR bitstream
  • The length of the PR bitstream

After verifying that the device is opened, the bitstream is of adequate length, and the PCIe endpoint of the device is reachable, the aclpci_pr function writes 0x1 to the PR IP status register. Then, the aclpci_pr function writes the complete bitstream, 32 bits at a time, to the PR IP. After the bitstream transfer is complete, the aclpci_pr function performs a read operation to the PR IP status register to verify whether PR is successful. A return value of 0x14 indicates a successful PR operation; any other return value indicates an error.

To override the default reconfiguration mechanism, set the ACL_PCIE_USE_JTAG_PROGRAMMING environment variable, as shown below:

  • For Windows, type set ACL_PCIE_USE_JTAG_PROGRAMMING=1 at the command prompt.
  • For Linux, type export ACL_PCIE_USE_JTAG_PROGRAMMING=1 at the command prompt.

Setting ACL_PCIE_USE_JTAG_PROGRAMMING specifies that JTAG full-chip configuration is the default mechanism for reconfiguring the device.