Intel® FPGA SDK for OpenCL™: Intel® Arria® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683267
Date 3/28/2022
Public
Document Table of Contents

3.7.2. Intel® Quartus® Prime Compilation Flow for Board Developers

The quartus_sh --flow compile top -c base command executes the Intel® Quartus® Prime compilation flow that generates a base.sof full-chip JTAG programming file within the .aocx file.

The script performs the necessary tasks to ensure that the import revision compilations using the timing-closed and locked-down static region are PR-compatible with each other.

Running the quartus_sh --flow compile top -c base command executes the following tasks:

  • Runs quartus_syn to execute the Analysis and Synthesis stage of the Intel® Quartus® Prime compilation flow.
  • Runs quartus_fit to execute the Place and Route stage of the Intel® Quartus® Prime compilation flow.
  • Runs quartus_sta to execute the Static Timing Analysis stage of the Intel® Quartus® Prime compilation flow.
  • Runs the INTELFPGAOCLSDKROOT/board/a10_ref/hardware/a10gx/scripts/post_flow_pr.tcl file.

    The post_flow_pr.tcl script determines the maximum frequency at which the OpenCL™ kernel can run and generates the corresponding PLL settings. The script then reruns static timing analysis. The script also exports the compilation database of the base revision compilation results as a forward-compatible Partition Database File (.qdb). Refer to the QDB File Generation section for more information.

  • Runs quartus_asm to generate the .sof file with updated embedded PLL settings. Updating the .sof file allows it to run safely on the board with the maximum kernel frequency.
  • Generates the fpga.bin file, which contains the full-chip programming file. The full-chip programming file (base.sof) is in the .acl.sof section of the fpga.bin file.

The .aocx file that the base revision compilation flow generates only contains the .sof full-chip programming file. It does not contain a programming file that can be used with PR because this .aocx file is only intended to be written to Flash memory as the default FPGA image. The Intel® FPGA SDK for OpenCL™ program utility automatically uses JTAG programming when it programs with a .aocx file from the base revision compilation. Only the import revision compilation flow, executed by the SDK user, generates a .aocx file that can be used with PR.