Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1. Partial Reconfiguration IP Core

Partial reconfiguration (PR) offers you the ability to reconfigure part of the design's core logic such as LABs, MLABs, DSP, and RAM, while the remainder of the design continues running. The PR IP core provides a standard interface to this ability and eliminates the need to manually instantiate an interface with the PR control block. You can instantiate the PR IP core through Platform Designer (Standard) or Platform Designer, or via the Intel® Quartus® Prime IP Catalog. The Intel® Quartus® Prime Standard Edition software supports the PR IP Core for the Stratix® V device family and Cyclone® V devices whose part number ends in "SC", for example, 5CGXFC9E6F35I8NSC.

You can perform partial reconfiguration through either an internal host residing in the core logic, or as an external host via dedicated device pins. The advantage of the internal host is that you store all the logic needed to perform PR on the device, without the need for external devices.

Figure 1. PR IP Core Components


When you instantiate the PR IP core, the Main Controller module is instantiated. This module includes the Control Block (CB) Interface Controller, Freeze/Unfreeze Controller, Bitstream Decoder, and the Data Source Controller. A Data Source Interface module provides you with an optional JTAG Debug Interface and PR Data Interface. If you choose to use the PR IP core in internal host mode, the IP core automatically instantiates the corresponding crcblock and prblock WYSIWYG atom primitives.

If used as external host (placed in another FPGA or CPLD), the PR IP core provides the required interface ports. Connect to the dedicated PR pins and CRC_ERROR pin on the target FPGA undergoing partial reconfiguration.

Figure 2. Managing Partial Reconfiguration with an Internal or External Host


The figure shows how to connect these blocks to the PR control block (CB). In your system, you include either the external host or the internal host, but not both. During PR, the PR Control Block (CB) is in Passive Parallel x16 programming mode for 28nm devices. In external host mode, the PR control block is not instantiated in the core of the device undergoing PR, because there is a direct connection from the external PR pins to the internal control block.

You can instantiate the PR IP core as the internal host for all supported devices. When you specify it as the internal host, both prblock and crcblock WYSIWYG atom primitives are auto-instantiated as part of the design. You can instantiate the PR IP core as the external host on any supported devices, as specified in the device family list.

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