Quartus® Prime Pro Edition User Guide: Timing Analyzer

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ID 683243
Date 11/26/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Timing Analysis Introduction 2. Using the Quartus® Prime Timing Analyzer 3. Troubleshooting Common Timing Issues A. Quartus® Prime Pro Edition User Guides
1. Timing Analysis Introduction x
1.1. Timing Analysis Basic Concepts 1.2. Timing Analysis Overview Document Revision History
1.1. Timing Analysis Basic Concepts x
1.1.1. Timing Path and Clock Analysis 1.1.2. Clock Setup Analysis 1.1.3. Clock Hold Analysis 1.1.4. Recovery and Removal Analysis 1.1.5. Multicycle Path Analysis 1.1.6. Metastability Analysis 1.1.7. Timing Pessimism 1.1.8. Clock-As-Data Analysis 1.1.9. Multicorner Timing Analysis 1.1.10. Time Borrowing
1.1.1. Timing Path and Clock Analysis x
1.1.1.1. The Timing Netlist 1.1.1.2. Timing Paths 1.1.1.3. Data and Clock Arrival Times 1.1.1.4. Launch and Latch Edges
1.1.5. Multicycle Path Analysis x
1.1.5.1. Multicycle Clock Hold 1.1.5.2. Multicycle Clock Setup
1.1.10. Time Borrowing x
1.1.10.1. Time Borrowing Limitations 1.1.10.2. Time Borrowing with Latches 1.1.10.3. Enabling Time Borrowing Optimization
2. Using the Quartus® Prime Timing Analyzer x
2.1. Using Timing Constraints throughout the Design Flow 2.2. Timing Analysis Flow 2.3. Applying Timing Constraints 2.4. Timing Constraint Descriptions 2.5. Timing Report Descriptions 2.6. Scripting Timing Analysis 2.7. Using the Quartus® Prime Timing Analyzer Document Revision History 2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.2. Timing Analysis Flow x
2.2.1. Step 1: Specify General Timing Analyzer Settings 2.2.2. Step 2: Specify Timing Constraints 2.2.3. Step 3: Run the Timing Analyzer 2.2.4. Step 4: Analyze Timing Reports
2.2.2. Step 2: Specify Timing Constraints x
2.2.2.1. Specifying SDC-on-RTL Timing Constraints 2.2.2.2. Specifying Conventional SDC Timing Constraints 2.2.2.3. Specifying Synthesis-Only SDC Timing Constraints
2.2.3. Step 3: Run the Timing Analyzer x
2.2.3.1. Running Post-Synthesis Early Timing Analysis 2.2.3.2. Running Post-Fit Timing Analysis
2.2.3.2. Running Post-Fit Timing Analysis x
2.2.3.2.1. Setting the Operating Conditions for Timing Analysis 2.2.3.2.2. Promoting Critical Warnings to Errors
2.2.4. Step 4: Analyze Timing Reports x
2.2.4.1. Cross-Probing with Design Assistant 2.2.4.2. Launching Design Assistant from Timing Analyzer 2.2.4.3. Locating Timing Paths in Other Tools 2.2.4.4. Correlating Constraints to the Timing Report
2.2.4.1. Cross-Probing with Design Assistant x
2.2.4.1.1. Cross-Probing from Design Assistant to Timing Analyzer
2.3. Applying Timing Constraints x
2.3.1. Recommended Initial Conventional SDC Constraints 2.3.2. Example Circuit and Conventional SDC File 2.3.3. SDC File Precedence 2.3.4. Iteratively Modifying Constraints 2.3.5. Applying Entity-Bound Timing Constraints 2.3.6. Constraining Design Partition Ports 2.3.7. Using Fitter Overconstraints
2.3.1. Recommended Initial Conventional SDC Constraints x
2.3.1.1. Create Clock (create_clock) 2.3.1.2. Derive PLL Clocks (derive_pll_clocks) 2.3.1.3. Derive Clock Uncertainty (derive_clock_uncertainty) 2.3.1.4. Set Clock Groups (set_clock_groups)
2.3.5. Applying Entity-Bound Timing Constraints x
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints 2.3.5.2. Using Entity-Bound SDC Files
2.3.5.1. Using Entity-Based SDC-on-RTL Constraints x
2.3.5.1.1. Targeting Constraints to Module Inputs and Outputs 2.3.5.1.2. Entity Based SDC-on-RTL Constraint Scope 2.3.5.1.3. Automatic Scope Example for SDC-on-RTL 2.3.5.1.4. Manual Scope Example for SDC-on-RTL
2.3.5.2. Using Entity-Bound SDC Files x
2.3.5.2.1. Entity-Bound SDC Constraint Scope 2.3.5.2.2. Automatic Scope Entity-bound Constraint Example 2.3.5.2.3. Manual Scope Entity-bound Constraint Example 2.3.5.2.4. Exporting a Design Partition with Entity-bound Constraints 2.3.5.2.5. Importing a Design Partition with Entity-bound Constraints
2.3.6. Constraining Design Partition Ports x
2.3.6.1. Timing Analysis of Imported Compilation Results
2.4. Timing Constraint Descriptions x
2.4.1. Clock Constraints 2.4.2. I/O Constraints 2.4.3. Delay and Skew Constraints 2.4.4. Timing Exception Constraints 2.4.5. Delay Annotation
2.4.1. Clock Constraints x
2.4.1.1. Creating Base Clocks 2.4.1.2. Creating Virtual Clocks 2.4.1.3. Creating Generated Clocks (create_generated_clock) 2.4.1.4. Deriving PLL Clocks 2.4.1.5. Creating Clock Groups (set_clock_groups) 2.4.1.6. Accounting for Clock Effect Characteristics 2.4.1.7. Constraining CDC Paths
2.4.1.1. Creating Base Clocks x
2.4.1.1.1. Automatic Clock Detection and Constraint Creation
2.4.1.2. Creating Virtual Clocks x
2.4.1.2.1. Specifying I/O Interface Uncertainty 2.4.1.2.2. I/O Interface Clock Uncertainty Example
2.4.1.3. Creating Generated Clocks (create_generated_clock) x
2.4.1.3.1. Clock Divider Example (-divide_by) 2.4.1.3.2. Clock Multiplexer Example
2.4.1.5. Creating Clock Groups (set_clock_groups) x
2.4.1.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive) 2.4.1.5.2. Asynchronous Clock Groups (-asynchronous) 2.4.1.5.3. set_clock_groups Constraint Tips
2.4.1.6. Accounting for Clock Effect Characteristics x
2.4.1.6.1. Set Clock Latency (set_clock_latency) 2.4.1.6.2. Clock Uncertainty
2.4.2. I/O Constraints x
2.4.2.1. Deprecation of the blackbox Argument 2.4.2.2. Input Constraints (set_input_delay) 2.4.2.3. Output Constraints (set_output_delay)
2.4.3. Delay and Skew Constraints x
2.4.3.1. Advanced I/O Timing and Board Trace Model Delay 2.4.3.2. Maximum Skew (set_max_skew) 2.4.3.3. Net Delay (set_net_delay) 2.4.3.4. Data Delay (set_data_delay)
2.4.4. Timing Exception Constraints x
2.4.4.1. Timing Exception Precedence 2.4.4.2. False Paths (set_false_path) 2.4.4.3. Minimum and Maximum Delays 2.4.4.4. Multicycle Paths 2.4.4.5. Multicycle Exception Examples 2.4.4.6. Creating Efficient Timing Exceptions
2.4.4.4. Multicycle Paths x
2.4.4.4.1. Common Multicycle Applications 2.4.4.4.2. Relaxing Setup with Multicycle (set_multicyle_path) 2.4.4.4.3. Accounting for a Phase Shift (-phase)
2.4.4.5. Multicycle Exception Examples x
2.4.4.5.1. Default Multicycle Analysis 2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0 2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1 2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset 2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency 2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset 2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency 2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5. Timing Report Descriptions x
2.5.1. Report Fmax Summary 2.5.2. Report Timing 2.5.3. Report Timing By Source Files 2.5.4. Report Data Delay 2.5.5. Report Net Delay 2.5.6. Report Clocks and Clock Network 2.5.7. Report Clock Transfers 2.5.8. Report Metastability 2.5.9. Report CDC Viewer 2.5.10. Report Asynchronous CDC 2.5.11. Report Logic Depth 2.5.12. Report Neighbor Paths 2.5.13. Report Register Spread 2.5.14. Report Route Net of Interest 2.5.15. Report Retiming Restrictions 2.5.16. Report Register Statistics 2.5.17. Report Pipelining Information 2.5.18. Report Time Borrowing Data 2.5.19. Report Exceptions and Exceptions Reachability 2.5.20. Report Bottlenecks 2.5.21. Check Timing 2.5.22. Report SDC
2.5.13. Report Register Spread x
2.5.13.1. Registers with High Timing Path Endpoint Tension 2.5.13.2. Registers with High Immediate Fan-Out Tension
2.5.20. Report Bottlenecks x
2.5.20.1. Specifying Custom Bottleneck Criteria
2.6. Scripting Timing Analysis x
2.6.1. The quartus_sta Executable 2.6.2. The quartus_staw Executable 2.6.3. Collection Commands
2.6.3. Collection Commands x
2.6.3.1. Wildcard Characters 2.6.3.2. Adding and Removing Collection Items 2.6.3.3. Query of Collections 2.6.3.4. Using the get_pins Command
3. Troubleshooting Common Timing Issues x
3.1. Troubleshooting Asynchronous Clock Domain Crossing (CDC) Timing Issues 3.2. Troubleshooting Reset Domain Crossing (RDC) Timing Issues 3.3. Troubleshooting Common Timing Issues Revision History
3.1. Troubleshooting Asynchronous Clock Domain Crossing (CDC) Timing Issues x
3.1.1. CDC Timing Overview 3.1.2. Identifying CDC Timing Issues Using Design Assistant 3.1.3. Identifying CDC Timing Issues Using Timing Reports 3.1.4. Debug CDC Example 1—Incorrect SDC Definition 3.1.5. Debug CDC Example 2—Additional Logic in the Crossing 3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
3.1.3. Identifying CDC Timing Issues Using Timing Reports x
3.1.3.1. Using Report Clock Transfers to Identify CDC Issues 3.1.3.2. Using Report Asynchronous CDC to Identify CDC Issues 3.1.3.3. Identifying Synchronizer CDC Issues
3.1.3.3. Identifying Synchronizer CDC Issues x
3.1.3.3.1. Reviewing Reports about Synchronizers 3.1.3.3.2. Constraining Synchronizers in CDCs
3.1.4. Debug CDC Example 1—Incorrect SDC Definition x
3.1.4.1. Resolve Violation: 1-Bit Asynchronous Transfer Not Synchronized 3.1.4.2. Resolve Violation: CDC Bus Constructed with Unsynchronized Registers 3.1.4.3. Resolve Violation: Intra-Clock False Path Synchronizer 3.1.4.4. Example 1 CDC Debug Summary
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing x
3.1.5.1. Resolve Violation: Combinational Logic Before Synchronizer Chain
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains x
3.1.6.1. Resolve Violation: Multiple Clock Domains Driving a Synchronizer Chain
3.2. Troubleshooting Reset Domain Crossing (RDC) Timing Issues x
3.2.1. RDC Timing Overview 3.2.2. Debug RDC Example—Asynchronous Reset Is Not Synchronized
3.2.2. Debug RDC Example—Asynchronous Reset Is Not Synchronized x
3.2.2.1. Resolve Violation: Asynchronous Reset Is Not Synchronized
Answers to Top FAQs
1. Timing Analysis Introduction
2. Using the Quartus® Prime Timing Analyzer
3. Troubleshooting Common Timing Issues
A. Quartus® Prime Pro Edition User Guides

1.1.1. Timing Path and Clock Analysis

The Timing Analyzer measures the timing performance for all timing paths identified in your design. Prior to running full timing analysis, you can run post-synthesis early timing analysis to obtain an early view of the design core timing. For post-fit timing analysis, the Timing Analyzer requires a timing netlist that describes your design's nodes and connections for analysis and uses routing delays between core blocks represented by average interconnect delays. The post-synthesis timing delays reflect the delays of each type of connected core block.

Post-fit timing analysis also determines clock relationships for all register-to-register transfers in your design by analyzing the clock setup and hold relationship between the launch edge and latch edge of the clock.


Section Content
The Timing Netlist
Timing Paths
Data and Clock Arrival Times
Launch and Latch Edges

Level Two Title