Visible to Intel only — GUID: mwh1410383775183
Ixiasoft
Visible to Intel only — GUID: mwh1410383775183
Ixiasoft
2.4.4.4.2. Relaxing Setup with Multicycle (set_multicyle_path)
In the following example, the source clock has a period of 10 ns, but the clock enable signal controls a group of latching registers, so the registers only enable every other cycle. The 10 ns clock feeds registers , so the Timing Analyzer reports a setup of 10 ns and a hold of 0 ns. However, the data is transferring every other cycle, so the Timing Analyzer must analyze the relationships as if the clock is operating at 20 ns. The result is a setup of 20 ns, while the hold remains 0 ns, thus extending the window for data recognition.
The following pair of multicycle assignments relax the setup relationship by specifying the -setup value of N and the -hold value as N-1. You must specify the hold relationship with a -hold assignment to prevent a positive hold requirement.
Constraint to Relax Setup and Maintain Hold
set_multicycle_path -setup -from src_reg* -to dst_reg* 2 set_multicycle_path -hold -from src_reg* -to dst_reg* 1
You can extend this pattern to create larger setup relationships to ease timing closure requirements. A common use for this exception is when writing to asynchronous RAM across an I/O interface. The delay between address, data, and a write enable may be several cycles. A multicycle exception to I/O ports allows extra time for the address and data to resolve before the enable occurs.
The following constraint relaxes the setup by three cycles:
Three Cycle I/O Interface Constraint
set_multicycle_path -setup -to [get_ports {SRAM_ADD[*] SRAM_DATA[*]} 3 set_multicycle_path -hold -to [get_ports {SRAM_ADD[*] SRAM_DATA[*]} 2